Manufacturing method of self-alignment low-voltage super-junction MOFET

Abstract

The invention discloses a manufacturing method of a self-alignment low-voltage super-junction MOFET. A terminal region deep trench formed on n-type epitaxy surrounds an active area deep trench; field oxides grow on the bottom sand the side walls of the deep trenches; primary polycrystalline silicon deposition is carried out; etching is carried out till polycrystalline silicon is flush with the upper surface of an epitaxial layer; secondary polycrystalline silicon deposition is carried out; secondary polycrystalline silicon dry method back etching is carried out to form a shallow slot MOSFET device grid; a P trap is formed; a high-thickness oxidation layer is formed, and the oxidation layer is removed; a device active area is manufactured; contact hole etching is carried out, a light resistor of the whole active area of a small cell area is switched on, a light resistor of a terminal hole demand area is switched on, and small cell area self-alignment hole etching is carried out; ohmic contact is formed through contact hole etching injection, and finally the structure is completed. On the premise of keeping the process cost unchanged, the area of a source area and a single cell can be reduced, and the whole chip area can be reduced.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and in particular relates to a method for manufacturing a self-aligned low-voltage super-junction MOSFET. Background technique [0002] For traditional power MOSFET devices, there is a certain trade-off relationship between device on-resistance (Ron) and source-drain breakdown voltage (Ron∝BV 2.5 ), has limited the development of power MOSFET devices for a long time. The low-voltage super-junction MOSFET uses the principle of charge balance, so that the N-type drift region can achieve a higher breakdown voltage of the device even under the condition of a higher doping concentration, thereby obtaining a low on-resistance, breaking the traditional silicon power MOSFET. limit. However, due to the development of small-scale devices, the small-scale is becoming more and more stringent for the photolithographic alignment process. [0003] In addition to the good electrical perfor...

AI Technical Summary

Problems solved by technology

[0004] At present, in the production and manufacture of large-sized low-voltage super-junction MOSFETs, the source area is large, and there is no problem with hole alignment. However, with the development of small-scale technology, the reduction of source area increases the difficulty of photolithographic alignment of factory holes. If it is not accurate, it will cause device failure or abnormal device parameters.

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