Low-temperature wafer-level packaging method for lateral interconnection for RF mems device applications
A wafer-level packaging and device technology, which is applied to electric solid devices, semiconductor devices, and processes for producing decorative surface effects, etc., can solve the problem that the packaging strength and air tightness of organic materials cannot be guaranteed, and the process difficulty and process cost are increased. , Unable to realize the horizontal interconnection of leads, etc., to achieve the effect of strong plasticity, low cost and easy realization
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[0057] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.
[0058] Such as Figures 1 to 4 The low-temperature wafer-level packaging method for lateral interconnection for the application of RF MEMS devices, which includes the fabrication of the package cover 1, the fabrication of the package substrate 2, and the alignment and bonding of the package cover 1 and the package substrate 2, which is unique at:
[0059] The fabrication of the package cover plate 1 includes the following steps:
[0060] First, choose a silicon wafer, or non-silicon material such as glass, or GaN, as the package cover material. After cleaning, a bonding wire pattern mask is photoetched.
[0061] Next, 20 to 50 nm of Ti is used as an adhesion layer by t...
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