Statistics static state sequential analysis method applied to near/sub threshold digital circuit

Abstract

The invention discloses a statistics static state sequential analysis method applied to a near / sub threshold digital circuit; the method comprises the following steps: reducing the standard cell library work voltage to near the threshold-voltage, and carrying out function simulation and characterization modeling for a near / sub threshold standard cell library; using a probability time-delay analysis algorithm to fast parse and rank path time-delays; using a Monte Carlo parse strategy and 3 [sigma] decision standard to concisely parse a suspected path, thus further improving sequential reliability. The provided accurate, reliable and fast statistics static state sequential analysis method can solve near / sub threshold digital circuit sequential analysis reliability problems, fully considers technology deviation influences on the path sequence, thus solving the near / sub threshold digital circuit sequential analysis reliability problems; compared with a conventional static state sequential analysis method and a Hspice-based sequential simulation method, the statistics static state sequential analysis method has obvious advantages on sequential analysis accuracy and efficiency.

Description

Technical field [0001] The present invention relates to the field of low power consumption integrated circuit design, in particular to a statistical static time sequence analysis method applied to near / sub-threshold digital circuits. Background technique [0002] With the continuous improvement of single-chip integration, power consumption has become a key factor restricting the development of integrated circuits. Reducing the operating voltage of the chip has always been the most effective low-power technology. The traditional technology has very limited voltage reduction, and the true operating voltage of the chip is often higher than the threshold voltage. The sub-threshold technology is to reduce the working voltage of the chip to or below the threshold, and only use the weak current in the sub-threshold state to drive the circuit to achieve extremely low power consumption. [0003] However, due to the influence of process deviation, the stability of the near / sub-threshold cir...

AI Technical Summary

Problems solved by technology

[0003] However, due to the influence of process deviation, the stability of near / sub-threshold circuits is severely deteriorated, making the timing analysis of near / sub-threshold digital circuits extremely complicated, as follows:

[0004] 1) The process deviation leads to a scattered probability distribution of the standard cell delay, and it is difficult to accurately fit this distribution trend with an expression;

[0005] 2) The local process deviation makes the delay variation trend of each standard unit non-consistent, resulting in a more complex distribution state of the data path delay;

[0007] Obviously, the timing analysis method based on the traditional process angle has been invalidated. Although the Hspice simulation tool can be used to quantitatively analyze the impact of process deviation on path delay, it is very time-consuming and not feasible for large-scale digital circuits.

[0008] Therefore, there is an urgent need for a fast and accurate timing analysis method for near / subthreshold digital circuits to solve the timing reliability and stability problems

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