DDR (Double Data Rate) time sequence and delay skew simulation evaluation method based on lookup table

Abstract

The invention discloses a DDR (Double Data Rate) time sequence and delay skew simulation evaluation method based on a lookup table. The time sequence simulation evaluation method comprises the following steps: step 1), performing time sequence simulation in advance on signal lines of various signal transmission component types and delay physical property types, and obtaining a unit length delay lookup table of the signal lines; step 2), dividing signal lines of signals to be analyzed into signal line sub segments, and determining the delay physical property type and line length of each signal line sub segment; step 3), obtaining the signal delay of each signal line sub segment by the lookup table; and step 4), summarizing the delays of various signal line sub segments and obtaining a total delay of the signals to be analyzed; the delay skew simulation evaluation method subtracts the total delay of two signals to be analyzed and calculates the delay skews of the two signals to be analyzed. The DDR time sequence and delay skew simulation evaluation method based on the lookup table provided by the invention can simply and quickly perform simulation evaluation on the DDR signal delay and skew, and provide fast and accurate time sequence evaluation and design reference for the DDR signal design in view of the influences of different signal transmission components and delay physical properties.

Description

technical field [0001] The invention relates to DDR timing simulation technology, in particular to a look-up table-based DDR timing and delay skew simulation evaluation method. Background technique [0002] With the development of microelectronics technology, the performance of microprocessors is getting higher and higher. In order to improve the memory access bandwidth and reduce the performance gap between the processor and the memory, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is widely used in the memory bus design of electronic communication systems. As a typical parallel bus structure, DDR technology improves memory access speed and bandwidth, and meets the needs of high-speed data transmission. However, the continuous upgrading of DDR technology makes the timing problem in system design more and more prominent, which not only poses a severe challenge to system design, but even becomes a bottleneck that limits the further increase of DDR tra...

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Problems solved by technology

Existing methods cannot meet the above two requirements at the same time

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