Graphical silicon-on-insulator substrate material and preparation method thereof

Abstract

The invention provides a graphical silicon-on-insulator (SOI) substrate material and a preparation method thereof. The preparation method comprises the steps of 1) providing an SOI substrate comprising bottom silicon, a buried oxide layer and top silicon, and forming an insulating layer on the surface of the top silicon; 2) forming an etching window corresponding to a position for preparing a transistor channel; 3) etching the insulating layer to form a groove penetrating through the top silicon; 4) providing a silicon substrate, and bonding the silicon substrate and the insulating layer; 5) removing the bottom silicon; and 6) removing the buried oxide layer. The groove is formed in the insulating layer corresponding to the position for preparing the transistor channel, and the groove completely penetrates through the space between the top silicon and the bottom silicon, so that a hollowed area is formed below the transistor channel prepared later. In the substrate preparation process, annealing and peeling steps in a Smart-cut method are avoided while the quality of the material is guaranteed, so that the problem of breakage of the top silicon in the graphical area due to high stress is solved.

Description

technical field [0001] The invention relates to a semiconductor device substrate and a preparation method thereof, in particular to a patterned silicon-on-insulator substrate material and a preparation method thereof. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, SOI has gradually become a deep submicron low-voltage, low-voltage Th...

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Problems solved by technology

[0008] First, there is a certain parasitic capacitance between the source drain and the substrate, which affects the device speed;

[0009] Second, the source-drain is coupled through the underlying BOX, which is prone to short-channel effects in smaller-sized devices;

[0010] Third, the defects in the insulating layer below the channel will scatter the channel carriers and affect the mobility of the carriers;

[0011] Fourth, after high-energy particles are incident, electron-hole pairs will be excited in the BOX insulating layer, which will affect the radiation resistance of the device

[0012] In addition, the existing substrate material manufacturing process often requires the introduction of separation technologies such as Smart-cut. Smart-cut requires annealing and peeling during the separation process. For SOI substrate materials with patterned cavity structures, the top silicon is vulnerable Local damage due to high stress

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