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Device for building checkpoints for heterogeneous memory system

A technology for heterogeneous memory and system establishment. It is applied in memory systems, memory architecture access/allocation, memory address/allocation/relocation, etc., and can solve problems such as high overhead of checkpoint technology and useless writes.

Active Publication Date: 2016-08-24
HUAZHONG UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0024] The present invention provides a device for establishing a checkpoint for a heterogeneous memory system, which solves the problems of excessive overhead and a large number of useless writes in the existing storage-based checkpoint technology for heterogeneous memory

Method used

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  • Device for building checkpoints for heterogeneous memory system
  • Device for building checkpoints for heterogeneous memory system
  • Device for building checkpoints for heterogeneous memory system

Examples

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Embodiment Construction

[0088] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0089] like figure 1 As shown, the present invention includes a heterogeneous memory management module, an address mapping module, a derived page management module, and a checkpoint scheduling module.

[0090] like figure 2 As shown, the heterogeneous memory management module performs the following operations:

[0091] (1) Wait for the user's memory access request, and perform step (2) after receiving the memory access request;

[0092] (2) Detect whether cache has the page that the physical address Ar in the memory access request will visit in DRAM, then give corresponding page address in DRAM to DRAM address Ad, carry out step (3), otherwise turn step (4);

[0093] (3) forward the memory access request to DRAM: give Ad the value of Ad+Ar mod Sp, then, change the physical address Ar in the memory access request into Ad, send this memory a...

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PUM

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Abstract

The invention discloses a device for building checkpoints for a heterogeneous memory system, and belongs to the technical field of system fault tolerance of the computer system structure. The device solves the problem that the checkpoints based on storage for heterogeneous memory are overlarge in technical overhead and have a great deal of useless write-in. The device comprises a heterogeneous memory management module, an address mapping module, a derivative page management module, and a checkpoint dispatching module. The heterogeneous memory management module controls data of heterogeneous memory moving between a DRAM and an NVM. The address mapping module provides fine-grit and low-overhead address mapping strategies, when request tries to modify data of the checkpoints, the address mapping module will have the request mapped to other hardware addresses so as to keep consistency of data in checkpoints. The derivative page management module controls derivative pages. The checkpoint dispatching module controls when to trigger the checkpoints. The device is transparent to upper applications that memory usage and redundant write-in are effectively reduced, useless write-in is reduced during checking consistency of the checkpoints, and system operation time is shortened.

Description

technical field [0001] The invention belongs to the system fault-tolerant technology of computer system structure, and in particular relates to a device for establishing checkpoints for heterogeneous memory systems. Background technique [0002] Checkpoint technology is a technology commonly used in the field of system fault tolerance. It saves information such as working data and central processing unit (CPU) status in the system memory as checkpoints to non-volatile storage media. When the system encounters a failure, The information in the checkpoint can restore the system to the state when the checkpoint is established. [0003] Traditional memory-based checkpoint technology stores checkpoints in hard disks or solid-state disks. Limited by the read and write performance of hard disks and solid-state disks, memory-based checkpoint technology is difficult to perform at high frequencies, which limits the fault tolerance of the system. The memory checkpoint technology can s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06G06F12/0802G06F11/14
CPCG06F11/1448G06F12/0638G06F12/0802G06F2212/305
Inventor 吴松高翔金海
Owner HUAZHONG UNIV OF SCI & TECH
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