Transistors and methods of forming them

Abstract

The invention relates to a transistor and a formation method thereof. The formation method of the transistor comprises the steps of providing a substrate, forming a gate structure at the surface of the substrate, wherein the gate structure comprises a gate dielectric layer, a protection layer located at the surface of the gate dielectric layer and a gate layer located at the surface of the protection layer, forming a first side wall at the side wall surface of the gate structure, etching the substrate around the gate structure and the first side wall by adopting an over etching process so as to enabling the surface of the substrate to be lower than the bottom surface of the gate structure, and forming a second side wall at the surface of the first side wall after the first over etching process. The formed transistor is improved in shape and stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, is continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements, and transistor devices are one of the important components of MOS devices. [0003] For transistor devices, as the size of the transistor continues to shrink, the gate dielectric layer formed of silicon oxide or silicon oxynitride material in the prior art cannot meet the performance requirements of the transistor. In particular, transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer are prone to a series of problems such as leaka...

AI Technical Summary

Problems solved by technology

[0005] However, with the continuous shrinking of semiconductor process nodes, the size of the formed high-K metal gate transistors is continuously reduced, which leads to an increase in the process difficulty of manufacturing high-K metal gate transistors, and the performance of the formed high-K metal gate transistors is unstable.

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