Encapsulation structure, electronic equipment and encapsulation method

Abstract

The invention discloses an encapsulation structure which comprises a substrate, a fan-out unit and a wiring layer, wherein the fan-out unit comprises a first chip and a second chip; the first chip comprises a first pin array; the second chip comprises a second pin array; the fan-out unit also comprises a third pin array; the first pin array, the second pin array and the third pin array are opposite to the substrate; the wiring layer is bridged between the first pin array and the second pin array and used for connecting the first pins in the first pin array to corresponding second pin in the second pin array; the substrate is provided with a welding pad electrically connected with the wiring layer in the substrate; the third pin array is connected with the welding pad. The invention also discloses electronic equipment and an encapsulation method. The encapsulation structure disclosed by the invention has the advantages of low difficulty in production, low cost and miniaturization.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging, in particular to a packaging structure and a packaging method. Background technique [0002] With the continuous development of integrated electronic technology, the requirements for chip performance are also increasing, such as function enhancement, size reduction, energy consumption and cost reduction, etc., thus giving birth to 3DIC (three-dimensional integrated circuit) technology and 2.5DIC packaging technology. Silicon Interposer technology is a technical solution to realize the interconnection between wafers (Die) and the interconnection between wafers and substrates in three-dimensional integrated circuits and 2.5DIC packaging technologies. [0003] Taking the 2.5DIC package as an example, the 2.5DIC package in the prior art is to integrate at least two wafers into a fan-out unit (FanoutUnit) through the fan-out round-level packaging technology, and the fanout unit is pa...

AI Technical Summary

Problems solved by technology

[0004] It can be seen that the implementation scheme of 2.5DIC package in the prior art has the disadvantages of difficult process and high production cost

Moreover, the size of the silicon interposer is larger than the sum of all wafer sizes. The large-sized silicon interposer leads to high consumption (that is, high cost), which further increases the cost of 2.5DIC packaging, and is not conducive to the miniaturization of the packaging structure.

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