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Method for reducing influence of base reflection through exposure auxiliary graph

A technology for assisting graphics and substrates, which is applied to the originals for photomechanical processing, photolithography on patterned surfaces, optics, etc., and can solve problems such as collapse and size deviation of photoresist patterns

Active Publication Date: 2016-06-08
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to address the above-mentioned defects in the prior art, provide a method that can use exposure auxiliary patterns to reduce the influence of substrate reflection, and can solve the problem of photoresist pattern size deviation caused by bottom reflected light, or even collapse due to too narrow defect problem

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  • Method for reducing influence of base reflection through exposure auxiliary graph

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Embodiment Construction

[0020] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

[0021] figure 1 A flow chart of a method for reducing the influence of substrate reflection by using exposure assist patterns according to a preferred embodiment of the present invention is schematically shown.

[0022] Such as figure 1 As shown, the method for reducing the influence of substrate reflection by using an exposure assist pattern according to a preferred embodiment of the present invention includes:

[0023] The first step S1: Classify the boundary of the layout pattern of the ion implantation layer according to the distance from the photoresist boundary to the front active region layer and the polysilicon layer in the photoresist open area, wherein the distance is less than or equal to the distance threshold The layout graphic bo...

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Abstract

The invention provides a method for reducing the influence of base reflection through an exposure auxiliary graph. The method comprises the following steps: classifying ion implanted layer layout graphic boundaries according to the distances from a photoresist boundary to a front layer active region layer and a polysilicon layer within a photoresist opened region, classifying the ion implanted layer layout graphic boundaries with the distance smaller than or equal to a distance threshold as a first class, and classifying the ion implanted layer layout graphic boundaries with the distance greater than the distance threshold as a second class; adding an auxiliary graph with a second size to the second class of ion implanted layer layout graphic boundaries, which can expose a graph on a silicon wafer; adding an auxiliary graph with a first size on the first class of ion implanted layer layout graphic boundaries, which cannot expose a graph on the silicon wafer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for reducing the influence of substrate reflection by using exposure auxiliary patterns. Background technique [0002] With the continuous reduction of technology nodes, the pattern size of the ion implantation layer and the alignment accuracy requirements with the front layer are getting higher and higher. In the photolithography process, the ion implantation layer is affected by the reflection of the complex front layer pattern at the bottom, which will cause the photoresist pattern to deviate in size, or even collapse to cause defects if it is too narrow. Although the use of bottom anti-reflective coating (BARC) can reduce the influence of substrate reflection, it requires an additional etching process to remove BARC, which not only increases the cost, but also greatly increases the difficulty of the process. The size compensa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F1/36H01L21/027
CPCG03F1/36H01L21/0276
Inventor 张月雨倪晟于世瑞
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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