High-efficiency coarse granularity reconfigurable computing system

Abstract

The invention discloses a high-efficiency coarse granularity reconfigurable computing system for executing the serial executing part and parallel executing part of a source code; the parallel executing part is converted into configuration information; the invention comprises a general processor kernel, a coarse granularity reconfigurable array, a main memory, a shared memory and a configuration information memory; the coarse granularity reconfigurable array executes the parallel executing part and comprises a plurality of executing units arranged in array mode; every executing unit comprises three multiplexers, an operator and a register file; the multiplexers receive input data; the operator executes operation, outputs the operation result out of the array, outputs to any one executing unit of the next line and outputs to the register file. The coarse granularity reconfigurable computing system of the invention is wide in applicable type and low in hardware cost, ensures good performance, saves the configuration time and promotes the efficiency.

Description

technical field [0001] The invention relates to the technical field of processor structure design, in particular to an efficient coarse-grained reconfigurable computing system. Background technique [0002] With the development of microelectronics process technology, the limit of semiconductor device technology has been touched. Moore's Law, which has dominated the semiconductor industry for many years, has expired, and it is difficult to further increase the main frequency of microprocessors. However, the development of microelectronics process technology has also brought another progress, that is, the rapid improvement of on-chip integration. Therefore, the development of the current processor architecture has shifted from the pursuit of increasing the main frequency to how to make better use of increasingly abundant system-on-chip resources. [0003] Reconfigurable computing structure is a computing architecture different from the traditional von Neumann structure, also ...

AI Technical Summary

Problems solved by technology

[0014] 1. There is a storage wall problem: the system architecture design is unbalanced, the access bandwidth of the main memory channel is not enough, the local memory in the reconfigurable array is lacking, and the memory access is not flexible enough, making memory access a bottleneck of the system. Although a large number of computing units are configured, the The acceleration effect is limited;

[0015] 2. The configuration efficiency is not high: Although most reconfigurable architectures support dynamic reconfiguration, the number of cycles required to complete a configuration is too large, so frequent dynamic configurations cannot be performed;

[0016] 3. The interconnection structure is not flexible enough: the grid structure and its variants are often used, and it is difficult to access the cells near the center in the reconfigurable array. At the same time, the types of cells in the grid may be different, which do not match the requirements of the application, affecting more Mapping of various kinds of applications on reconfigurable architecture

Images