High voltage starting circuit with adjustable starting time

Abstract

The invention relates to a high voltage starting circuit with adjustable starting time. A drain electrode of a first N-channel metal oxide semiconductor (NMOS) transistor is connected to a first end of a first resistor, a grid electrode of a second NMOS transistor and a negative end of a diode. A source electrode of the first NMOS transistor and a positive end of the diode are connected to a power ground. The drain electrode of the second NMOS transistor and a second end of the first resistor are connected to an SW port of a chip. The source electrode of the second NMOS transistor and the first end of a second resistor are connected to a power supply port VDD of the chip. The second end of the second resistor is connected to the first end of a third resistor and a first input end of a first comparator. An output end of the first comparator is connected to a first counter. The output end of the first counter is connected to a pulse width modulation (PWM) controller. The first comparator detects a VDD voltage level and generates a control signal Ctrl1. The first counter counts the rising edge or the falling edge of the Ctrl1, and generates initial start enable signals and restart enable signals which flexibly adjust the time of power-on starting of the chip and the time of restarting of the chip in an unusual situation.

Description

technical field [0001] The invention relates to a high-voltage start-up circuit with adjustable start-up time, which is suitable for power management integrated circuits and belongs to the technical field of power semiconductors. Background technique [0002] The working waveform corresponding to the start-up mode of the traditional start-up circuit, such as figure 1 At the beginning of the T1 time period, the system is powered on and started, and the VDD voltage continues to rise. At the end of the T1 time period, the VDD voltage reaches the threshold VTH1, and the chip works normally. The T2 time period is the normal working stage. At a certain moment in T2, an abnormal situation occurs, and the VDD voltage drops. When the VDD voltage drops to the threshold value VTH2, the undervoltage lockout signal UVLO becomes active, and the chip enters the abnormal restart stage T3. At the end of T3, the VDD voltage rises to VTH1 again, the chip works normally again and detects the a...

AI Technical Summary

Problems solved by technology

[0003] Although the traditional startup method can ensure the chip starts normally and restarts under abnormal conditions, the time for this startup method to start the chip when it is powered on and restart under abnormal conditions is fixed and cannot be adjusted, and the chip is powered on and restarted under abnormal conditions. same speed

For example, if the power-on starts quickly, the restart time under abnormal conditions will also be very short, which will lead to large input power and large power loss during restart under abnormal conditions; if in order to reduce power consumption under abnormal conditions, slow down If the restart speed is lower, the power-on startup speed will also slow down, which may not meet the application requirements.

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