PID-resistant crystalline silicon cell preparation method

A technology of crystalline silicon cells and silicon substrates, applied in the field of solar cells, can solve the problems that silicon nitride films cannot meet insulation requirements, PID attenuation, component output power decline, etc., achieve good passivation, reduce equipment costs, and reduce Effects of small PID phenomena

Inactive Publication Date: 2015-12-02
STATE GRID TIANJIN ELECTRIC POWER +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the conventional preparation steps of crystalline silicon solar cells are: texturing-diffusion-wet etching-PECVD-screen printing-sintering; the silicon nitride film of crystalline silicon solar cells produced by this process cannot meet the insulation requirements, and the PID attenuation phenomenon is very Seriously, the output power of the module drops significantly

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  • PID-resistant crystalline silicon cell preparation method
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Embodiment 1

[0019] A method for preparing an anti-PID crystalline silicon battery, comprising the steps of:

[0020] 1) The silicon substrate is cleaned, textured, diffused, and wet-etched;

[0021] 2) oxidizing the silicon substrate after wet etching through an ozone nitrogen gas mixture with an ozone concentration of 30ppm to form a silicon dioxide film on the silicon substrate;

[0022] 3) Deposit a layer of Si with a thickness of 80 nm and a refractive index of 2.01 on the surface of the silicon substrate treated in step 2) using PECVD equipment. 3 N 4 membrane;

[0023] 4) After screen printing and sintering, an anti-PID crystalline silicon battery is obtained, which is marked as 1#.

[0024] Wherein, the ozone nitrogen gas mixture in step 2) is sprayed onto the surface of the silicon substrate, the gas flow rate is 30 L / min, the passing speed of the silicon wafer is 2.3 m / min, and the reaction temperature is 50°C.

Embodiment 2

[0026] A method for preparing an anti-PID crystalline silicon battery, comprising the steps of:

[0027] 1) The silicon substrate is cleaned, textured, diffused, and wet-etched;

[0028] 2) oxidizing the silicon substrate after wet etching through an ozone nitrogen gas mixture with an ozone concentration of 35ppm to generate a layer of silicon dioxide film on the silicon substrate;

[0029] 3) Deposit a layer of Si with a thickness of 82.7 nm and a refractive index of 2.05 on the surface of the silicon substrate treated in step 2) using PECVD equipment. 3 N 4 membrane;

[0030] 4) After screen printing and sintering, an anti-PID crystalline silicon battery is obtained, which is marked as 2#.

[0031] Wherein, the ozone-nitrogen gas mixture in step 2) is sprayed onto the surface of the silicon substrate, the gas flow rate is 40 L / min, the passing speed of the silicon wafer is 2.1 m / min, and the reaction temperature is 55°C.

Embodiment 3

[0033] A method for preparing an anti-PID crystalline silicon battery, comprising the steps of:

[0034] 1) The silicon substrate is cleaned, textured, diffused, and wet-etched;

[0035] 2) oxidizing the silicon substrate after wet etching through an ozone-nitrogen gas mixture with an ozone concentration of 50 ppm to form a silicon dioxide film on the silicon substrate;

[0036] 3) Deposit a layer of Si with a thickness of 83 nm and a refractive index of 2.07 on the surface of the silicon substrate treated in step 2) using PECVD equipment. 3 N 4 membrane;

[0037] 4) After screen printing and sintering, an anti-PID crystalline silicon battery is obtained, which is marked as 3#.

[0038] Wherein, the ozone-nitrogen gas mixture in step 2) is sprayed onto the surface of the silicon substrate, the gas flow rate is 40 L / min, the passing speed of the silicon wafer is 2.2 m / min, and the reaction temperature is 65° C.

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Abstract

The invention discloses a PID-resistant crystalline silicon cell preparation method, and the method comprises the following steps: 1) carrying out washing, texturizing, diffusing and wet etching of a silicon substrate; 2) enabling the silicon substrate to pass through mixed gas (ozone and nitrogen) and to be oxidized after wet etching, wherein the ozone concentration of the mixed gas is from 25 ppm to 60 ppm; 3) depositing an Si3N4 film on the surface of the silicon substrate through PECVD equipment after the processing of step 2), wherein the thickness of the Si3N4 film is from 79 nm to 85 nm, and the refractive index is from 2.01 to 2.09; 4) obtaining a PID-resistant crystalline silicon cell after screen printing and sintering. According to the invention, an oxidization step is added between wet etching and PECVD of a conventional preparation method, thereby forming the Si3N4 film on the surface of the silicon substrate, and enabling PID testing results of a product to be lower than 1%.

Description

technical field [0001] The invention relates to the field of solar cells, in particular to a method for preparing an anti-PID crystalline silicon cell. Background technique [0002] In a photovoltaic system, for safety reasons, the aluminum frame of the module is usually grounded, so that the battery terminal will be in a negative voltage state. Driven by this negative pressure, the current flows from the ground terminal to the battery through the aluminum frame, glass and EVA. During this process, a large amount of positive charges will accumulate on the surface of the battery, causing the battery to fail. This is why the components are under high potential for a long time. Attenuation, English is potential induced degradation, PID for short. With the development of photovoltaic technology, the number of panels connected in series in large-scale photovoltaic systems is increasing. Under working conditions, some components will be in a high voltage state, usually reaching 6...

Claims

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Application Information

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IPC IPC(8): H01L31/18H01L31/0216H01L31/068
CPCH01L31/02167H01L31/068H01L31/1804H01L31/1868Y02E10/547Y02P70/50
Inventor 杨福君王海滨康健杜彬于欣郑丽娜田小禾
Owner STATE GRID TIANJIN ELECTRIC POWER
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