A Wear Leveling Method for Variable Resistive Memory Based on Software Compilation Layer

Abstract

The invention discloses a wear leveling method for a variable resistance memory based on a software compilation layer, which includes the following steps: 1. According to the characteristics of the program, the program is divided into multiple program areas, and the number of write operations of each variable is counted and variable size; 2. According to the size of the unoccupied memory space, dynamically configure the size of the variable resistance memory SLC and MLC; 3. Allocate appropriate addresses for each variable, and allocate high performance and lifespan for frequently written variables Long single-layer units, allocate multi-layer units with large capacity for infrequently written variables, 4. Execute the compiled program on the embedded system to obtain wear leveling on the variable resistance memory. The invention has the following technical effects: better wear balance, further improving the service life of the variable resistance memory; only requiring very low execution time and storage overhead, and no hardware overhead.

Description

technical field [0001] The invention belongs to the technical field of computer storage, and in particular relates to a wear leveling method of a variable resistance memory. Background technique [0002] General-purpose DRAM memory is limited by problems such as high energy consumption and difficult expansion of capacity. A new type of low energy consumption, large capacity, non-volatile memory is expected to replace traditional DRAM memory, such as memory bank memory and variable resistance memory (PCM). In particular, the variable resistance memory PCM can implement a multi-level cell (Multi-Level Cell, MLC), that is, one cell can store two or more bits. Compared with single-level cell (Single-Level Cell, SLC), MLC can obtain higher density and larger capacity. However, this advantage also comes at a corresponding cost, due to the need for more precise sensing and control of the resistance of the PCM cells, increased corresponding access delays and reduced lifetime. [...

AI Technical Summary

Problems solved by technology

Prior art one has following shortcoming: need the support on hardware

Disadvantages of prior art 2: monitoring memory page faults to calculate the corresponding benefit function value is unavoidable and will cause a lot of overhead; only based on memory page faults to regulate the conversion of MLC and SLC

These existing technologies have huge writing overhead and running overhead, and most of them require the support of hardware and operating system, thus limiting the practical application of variable resistance memory in embedded systems

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