High-voltage power device and forming method thereof

Abstract

The invention provides a high-voltage power device and a forming method thereof. The device comprises a first doped area having a first doped type; one or a plurality of device doped areas arranged in the upper surface of the first doped area, wherein the device doped area has a second doped type opposite to the first doped type; and one or a plurality of second doped areas of the second doped type, wherein one end of the second doped area is in electric contact with a corresponding device doped area, the other end of the second doped area longitudinally extends to the first doped area, and in the transverse direction, the second doped areas and the first doped areas are alternatively distributed. The impurity concentration of each second doped area changes in a non-linear manner with the change of the longitudinal depth, and the total impurity concentration of the second doped areas is lower than the total impurity concentration of the first doped areas. According to the invention, the withstand voltage of the device is stabilized, and the conduction resistance of the device is reduced.

Description

technical field [0001] The invention relates to a high-voltage power device, in particular to a charge-compensated high-voltage power device and a forming method thereof. Background technique [0002] refer to figure 1 , figure 1 A high voltage MOS device structure in the prior art is shown. The high-voltage MOS device 100 includes: a first doped region 106 of the MOS device, the first doped region 106 is an N-type epitaxial region, and the first doped region 106 is drawn out from the first electrode 101 via an N-type doped substrate 108 , forming the drain of the MOS device; the P-type well region 102 of the MOS device; the N-type doped region 105 of the MOS device, forming a source region; the P-type doping region 109 of the MOS device, forming a substrate contact region, and a P-type well The region 102 and the P-type doped region 109 are short-circuited by the second electrode 103 to form the source of the MOS device; the gate 104 of the MOS device; the second doped r...

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Problems solved by technology

[0007] use figure 2 Although the compensation matching degree of the device decreases and a small part of the withstand voltage is sacrificed, the tolerance of the charge compensation is improved, that is, when the impurity concentration in the compensation region does not reach the best matching degree, the first doped region 206 and the The impurity concentration of the second doped region 210 can obtain a higher withstand voltage within a certain deviation range, which solves the situation of unstable withstand voltage

[0008] As mentioned above, although the methods proposed in US patent documents US6630698 and US6894329 have solved the problem of withstand voltage stability, due to the monotonous linear increase in concentration, in the area near the second electrode, the concentration of the second doped region is higher than that of first doped region

When the device is turned on, the current channel formed by the first doped region is narrowed in this region by the increase of the impurity concentration of the second doped region, that is, the so-called JFET resistance increases, resulting in an increase in the on-resistance of the device, The current capability of the device degrades

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