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Task scheduling method in heterogeneous multi-core architecture

A task scheduling and heterogeneous multi-core technology, which is applied in the directions of multi-program device, program startup/switching, resource allocation, etc., can solve the problem of low technology maturity, not widely used, non-master-slave heterogeneous multi-core system implementation Complicated problems, to achieve the effect of good scalability, low call overhead, and meet real-time scheduling requirements

Inactive Publication Date: 2015-09-09
常州北大众志网络计算机有限公司 +1
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AI Technical Summary

Problems solved by technology

[0007] The implementation of the non-master-slave heterogeneous multi-core system is complex and the technology maturity is not high. One example is the HSA architecture (Heterogeneous System Architecture) promoted by AMD, which has not been widely used yet.

Method used

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  • Task scheduling method in heterogeneous multi-core architecture

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Embodiment Construction

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments. These drawings are all simplified schematic diagrams, and only illustrate the basic structure of the present invention in a schematic manner, so they only show the structures related to the present invention.

[0023] figure 1 The flow chart of heterogeneous multi-core booting is shown: after the system chip is powered on, each processor core will jump to the booting address to start instruction fetch execution.

[0024] Since self-copying is required in the boot process of the auxiliary core, a memory access operation will occur, and this operation can only be performed after the main core completes the memory initialization. Therefore, the main core and the auxiliary core cannot independently complete their respective boot-up processes, and an interactive mechanism needs to be established to ensure the smooth progress of the following o...

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Abstract

The present invention relates to a task scheduling method in a heterogeneous multi-core architecture. Between a plurality of cores, data transmission is implemented in a manner of sharing a memory, and information transmission is implemented in a manner of interruption and polling; the shared memory is partitioned into a command area, a result area, a data input area and a data output area, and high-efficiency data structures are designed according to functions of these areas so as to establish a heterogeneous multi-core interactive memory model; and task scheduling adopts a plurality of circular queues to implement priority task queues, so that a high-efficiency fair task scheduling mechanism is implemented. The present invention provides a task scheduling method, which has high efficiency, good expandability and high portability, for the master-slave heterogeneous multi-core architecture. With the task scheduling method, load of a main core can be greatly reduced and integral load on a system chip can be balanced. Moreover, the task scheduling method is low in call overhead, which can not only efficiently meet the scheduling requirement of a single task, but also simultaneously meet the real-time scheduling requirement of a plurality of tasks.

Description

technical field [0001] The invention relates to the field of computer architecture, in particular to a task scheduling method oriented to a master-slave heterogeneous multi-core system. Background technique [0002] Over time, the demands on computing performance and energy efficiency have continued to increase. The improvement of the performance of early single-core processors benefited from the rapid development of semiconductor technology and large-scale integrated circuit technology. Today, due to the constraints of power consumption and design complexity, the performance improvement of single-core processors can no longer keep up with the needs of the times. [0003] The emergence of homogeneous multi-core processors provides a good solution for breaking through the performance bottleneck of single-core processors. Nowadays, homogeneous multi-core processors have become the mainstream in the development of processor design and manufacturing technology. Whether in mobi...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/48G06F9/50
Inventor 程旭刘锋张晟
Owner 常州北大众志网络计算机有限公司
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