Cache replacement method under heterogeneous memory environment

Abstract

The invention discloses a cache replacement method under heterogeneous memory environment. The method is characterized by comprising the steps: adding one source flag bit in a cache line hardware structure for flagging whether cache line data is derived from a DRAM (Dynamic Random Access Memory) or a PCM (Phase Change Memory); adding a new sample storage unit in a CPU (Central Processing Unit) for recording program cache access behaviors and data reusing range information; the method also comprises three sub methods including a sampling method, an equivalent position calculation method and a replacement method, wherein the sampling sub method is used for performing sampling statistics on the cache access behaviors; the equivalent position calculation sub method is used for calculating equivalent positions, and the replacement sub method is used for determining a cache line needing to be replaced. According to the cache replacement method, for the cache access characteristic of a program under the heterogeneous memory environment, a traditional cache replacement policy is optimized, the high time delay cost that the PCM needs to be accessed due to cache missing can be reduced by implementing the cache replacement method, and thus the cache access performance of a whole system is improved.

Description

technical field [0001] The invention belongs to the technical field of computer science, and more specifically relates to a cache replacement method in a heterogeneous memory environment. Background technique [0002] The development of traditional memory technology represented by Dynamic Random Access Memory (DRAM) has encountered a bottleneck in recent years. Restricted by the manufacturing process, it is becoming more and more difficult to obtain larger capacity DRAM memory at a lower cost; and as the capacity continues to increase, the problem of high energy consumption of DRAM memory is becoming increasingly prominent. The rise and development of new non-volatile memory (Non-Volatile Memory, NVM for short) technology provides an opportunity to break the traditional DRAM memory, which is the bottleneck of system performance and energy consumption. Non-volatile memory devices represented by Phase Change Memory (PCM) have good scalability, and are closer to the delay and ...

AI Technical Summary

Problems solved by technology

The quality of the cache replacement algorithm directly affects the efficiency of the cache, which in turn can affect the overall performance of the system

The traditional cache replacement algorithm represented by LRU and its derivative algorithm has achieved good performance in the traditional DRAM memory environment, but in the heterogeneous memory environment, the cache miss penalty (Miss Penalty) is inconsistent, that is, the DRAM and PCM The new feature of inconsistent access latency has not been fully considered in the traditional cache replacement algorithm, which raises the problem of improving cache usage efficiency in a heterogeneous memory environment

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