Field-programmable gate array testing method

Abstract

The invention discloses a field-programmable gate array testing method and belongs to integrated circuit design in the field of microelectronics and the field of electronic design automation. The method includes generating a testing circuit file according to a field-programmable gate array chip structure; generating a testing circuit constraint file according to the field-programmable gate array chip structure; obtaining an integrated net list according to the testing circuit constraint file; obtaining a mapping circuit net list according to the testing circuit constraint file and the integrated net list; completing routing of the testing circuit file according to a post-layout circuit unit and the testing circuit constraint file; obtaining a code stream file; testing an FPGA chip according to the code stream file. According to the field-programmable gate array testing method, the testing circuit is subjected to integration, mapping, layout, routing and code stream generation under constraint of the circuit constraint file, and the code stream file required by verification and testing is generated. The field-programmable gate array testing method is capable of effectively achieving wafer testing after FPGA layout verification and tape-out.

Description

technical field [0001] The invention belongs to the field of integrated circuit design and electronic design automation in the field of microelectronics, and in particular relates to a testing method of a field programmable gate array. Background technique [0002] The current wide-ranging FPGA (Field Programmable Gate Arrays, that is, Field Programmable Gate Arrays) is developing rapidly. SRAM-based FPGA products are mainly designed with bulk silicon, and mainstream products are basically monopolized by a few large companies such as Xilinx and Altera. However, there are relatively few advanced FPGA products used in special environments such as anti-radiation environments, and domestic procurement will be subject to foreign countries. This situation puts my country's national defense and aviation at a passive disadvantage in purchasing such special FPGA chips. [0003] Different from the test of ASIC (Application Specific Integrated Circuit) chip, the test of FPGA chip has gr...

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a field programmable gate array test method, which solves the technical problem of low test accuracy and effectiveness of the field programmable gate array chip in the prior art

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