Power transistor array structure with electrostatic protection circuit integrated

Abstract

The invention discloses a power transistor array structure with an electrostatic protection circuit integrated. Embedding of an electrostatic protection circuit formed by an SCR (silicon controlled rectifier) can be realized by partially replacing region sections of a drain region of a first unit structure of a power transistor with a region P+, and a grid electrode of the SCR is not connected with a grid electrode of the first unit structure but connected with a source electrode of the first unit structure. On the premise that performances of a power transistor array are unaffected and the process is unchanged, electrostatic protection capability of the power transistor array can be improved, false triggering accidents of the silicon controlled rectifier can be effectively reduced, and accordingly safety operation range of the power transistor array can be expanded. In addition, a grid gate structure of the SCR is designed to be recessed towards a drain side, and the region P+ is injected to a body region of a source side, so that the false triggering accidents of the silicon controlled rectifier can be further reduced, and the safety operation range of the power transistor array can be further expanded.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a power transistor array structure integrated with an electrostatic protection circuit. Background technique [0002] Power transistors are often used in high-voltage integrated circuits as output drive tubes that drive relatively large currents. Existing power drive tubes generally appear in the form of arrays. Such as Figure 1A Shown is a schematic diagram of the existing power transistor array layout structure; Figure 1B is along Figure 1A Schematic diagram of the cross-sectional structure of the unit structure at position A'A of ; a deep N well (DNW) 2 is formed on the silicon substrate 1, and the entire power transistor array is formed in the deep N well 2, and the unit of the power transistor Structure one is the NLDMOS device structure, including: [0003] A P-type body region 3 formed in the deep N well 2 . [0004] An N well 4 is formed in the deep N well 2 and...

AI Technical Summary

Problems solved by technology

Although embedding SCR can effectively improve the electrostatic protection capability of the output power transistor array, it will be a technical difficulty in this design to avoid false triggering of the SCR when the power transistor array is working normally. The higher the voltage and the higher the current, the easier it is for the SCR to trigger , so the embedded SCR will reduce the safe operating range (SOA) of the power transistor array

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