Improved full-digital successive approximation register delay lock loop (SARDLL) system

Abstract

The invention discloses an improved full digital successive approximation register delay lock loop (SARDLL) system. The SARDLL system comprises a 2-b SAR controller, a time sequence controller, three samplers, a one-hot coding encoder, a main RDCDL and two auxiliary RDCDLs. The SAR controller adopts the 2-b SAR algorithm to increase the lock speed of the SARDLL system. The main RDCDL is an improved RDCDL with 64 delay units. Each auxiliary RDCDL is an improved RDCDL with 16 delay units. Each delay unit in the improved RDCDL comprises two AND gates and two NOR gates. The SARDLL system increases the lock speed, meanwhile expands the working frequency range of the system, increases the maximum working frequency of the system, reduces chip area, reduces system power consumption and further improves the performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor and integrated circuit design, in particular to an improved all-digital successive approximation register delay-locked loop system. Background technique [0002] At present, the development of complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) technology has greatly increased the complexity and operating frequency of a System on Chip (SoC), resulting in a drastic increase in chip power consumption. Processors in multi-core system chips or portable electronic devices usually use Dynamic Voltage / Frequency Scaling (DVFS) technology to reduce operating power consumption, and the dynamic change of operating frequency is based on all-digital successive approximation registers. The clock skew elimination circuit (clock synchronization circuit) of the loop (Successive Approximation Register-controlled Delay-Locked Loop, SARDLL) poses new challenges: first, SARDLL...

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Problems solved by technology

[0003] In the existing technical solutions, the SARDLL system designed for DVFS SoC generally consists of a successive approximation register (Successive Approximation Register, SAR) controller, a resettable digitally controlled delay line (Resettable Digitally Controlled Delay Line, RDCDL), a timing controller, Composed of a phase detector, a sampler, a data selector and some buffers, the SARDLL system has two disadvantages: first, because the basic SAR controller is used, there is a problem that the locking speed is not fast enough, and the locking time is 3* N clock cycles of the input reference signal, where N is the number of digits of the SAR control word D; second, the delay line unit increases the chip area occupied by the delay line due to the use of two two-to-one data selectors, or due to The use of a pre-delay circuit (Prepositive Delay Circuit, PDC) limits the maximum operating frequency of the system

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