Pulse swallowing type clock synchronization circuit

Abstract

The invention discloses a pulse swallowing type clock synchronization circuit. The pulse swallowing type clock synchronization circuit comprises an edge trigger selection circuit and a stepping type variable delay circuit, wherein an input end of the edge trigger selection circuit is connected with a synchronization pulse input signal generated by a master chip, an input end of the stepping type variable delay circuit is connected with a synchronization pulse output signal generated by the master chip, an output end of the edge trigger selection circuit and an output end of the stepping type variable delay circuit are connected with an input end of an exclusive or gate so as to perform exclusive or operation, output of the exclusive or gate is detected through a pulse swallowing circuit, and then one path of the output is output through a synchronization clock, and the other path of the output is fed back to the stepping type variable delay circuit through a synchronization pulse generating circuit. The pulse swallowing type clock synchronization circuit does not need a high speed reset signal generation circuit, simplifies design of a circuit board, reduces complexity of a system, reduces cost of the system, and reduces debugging difficultly of the circuit board.

Description

technical field [0001] The invention relates to a pulse-swallowing clock synchronization circuit. Background technique [0002] At present, high-speed multi-channel data acquisition systems usually contain multiple data conversion chips. In most applications of this type of system, it is necessary to accurately align the data streams collected by each channel in time, so that the data collected by the multi-channel acquisition system There is the same or definite delay between the input analog signal to facilitate subsequent data processing and analysis, which requires the output signals of multiple data conversion chips distributed in different physical locations to flip at the same or definite moment, which requires multiple The clock signal inside the data conversion chip is strictly synchronized. [0003] In order to realize multi-chip clock synchronization, there are two traditional solutions: synchronous reset mode and pulse swallowing mode. The synchronous reset met...

AI Technical Summary

Problems solved by technology

The self-loop of the synchronization pulse signal and the path delay of the main chip synchronization pulse signal need to be strictly equal, which requires high requirements for circuit board design, especially when the clock frequency reaches GHz or higher, slight differences in circuit board wiring may cause synchronization failure

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