Wafer Level Packaging Method

Abstract

The invention discloses a wafer level packaging method. The wafer level packaging method includes that providing a substrate, wherein the substrate has a front surface and a back surface, and an interlevel dielectric layer and a welding pad located on the interlevel dielectric layer are formed in the front surface; forming a first through hole in the back of the substrate, wherein the interlevel dielectric layer exposes out of the first through hole; forming a polymer layer at each of the back surface of the substrate and the side wall of the first through hole; etching the interlevel dielectric layer, and etching to remove the polymer layers when etching the interlevel dielectric layer; repeating the steps of forming the polymer layer at each of the back surface of the substrate and the side wall of the first through hole, etching the interlevel dielectric layer, and etching to remove the polymer layers when etching the interlevel dielectric layer till exposing the welding pad, and forming a second through hole. According to the technical scheme, when etching the interlevel dielectric layer, the polymer layers protect the back of the substrate and the side wall of the first through hole from damage, the surfaces of the back of the substrate and the side wall of the first through hole are smooth, the electrical signals of wires in the second through hole are good, and the performance of the packaging structure is good.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer-level packaging method. Background technique [0002] Through Silicon Via (TSV for short) technology is an interconnection technology that realizes circuit conduction between chips, between substrates and substrates, or between substrates and chips. Unlike previous IC package bonding and overlay technologies using bumps, through-silicon via technology enables chips to be stacked in the three-dimensional direction with the highest density and the smallest size. [0003] An existing wafer-level packaging method based on TSV technology includes: [0004] refer to figure 1 , provide a substrate 1, the substrate 1 is a silicon substrate, the substrate 1 has a front S1 and a back S2, wherein the front S1 is bonded to the substrate 2, and there is a cavity 3 between them, and a device is formed on the front S1 of the substrate 1 structure, and an interlayer dielectric ...

AI Technical Summary

Problems solved by technology

[0009] The problem to be solved by the present invention is that, using the wafer-level packaging method based on TSV technology in the prior art, the TSV and the back of the substrate are damaged and uneven, which affects the electrical signal of the metal layer in the TSV, resulting in packaging Poor performance of the structure

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