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A kind of LED structure and manufacturing method thereof

A technology of LED structure and manufacturing method, applied in electrical components, circuits, semiconductor devices, etc., can solve the problems of high LED chip voltage, poor reliability, separation of P pads and extended electrode LED die, etc., to improve the expansion effect, The effect of improving luminous uniformity

Active Publication Date: 2017-03-01
HANGZHOU SILAN AZURE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The purpose of the present invention is to solve the problem in the prior art that the poor adhesion between the barrier layer and the extended electrodes leads to the detachment of the P pad and the extended electrodes from the LED die during packaging and wiring or in later applications
[0012] Another object of the present invention is to solve the problem of high LED chip voltage and poor reliability due to the thinning of the ITO extended electrode around the P pad in the prior art

Method used

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  • A kind of LED structure and manufacturing method thereof
  • A kind of LED structure and manufacturing method thereof
  • A kind of LED structure and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0057] Such as Figure 1A As shown, an epitaxial wafer is provided. The epitaxial wafer includes a substrate 11 and a stacked epitaxial structure formed on the substrate 11. The stacked epitaxial structure includes an N-type epitaxial layer 121 and an active layer 122 from bottom to top. and a P-type epitaxial layer 123, the substrate 11 is, for example, a sapphire substrate.

[0058] Such as Figure 1B As shown, an N-region mesa 1210 is fabricated on the stacked epitaxial structure through a conventional photolithography process, and the N-region mesa 1210 exposes the N-type epitaxial layer 121 . In this embodiment, the depth of the N-region mesa 1210 is greater than the sum of the thicknesses of the active layer 122 and the P-type epitaxial layer 123 but less than the sum of the thicknesses of the stacked epitaxial structure, that is, the thickness of the N-type epitaxial layer 121 The thickness of the N-type epitaxial layer 121 is smaller than that of other regions.

[0...

Embodiment 2

[0075] The difference between this embodiment and the first embodiment is that a high-resistance ITO thin film is formed on the P-type epitaxial layer by evaporation, and then an ITO barrier layer is formed by photolithography. In this embodiment, the high-temperature annealing process can be omitted, and a high-resistance ITO thin film is directly formed on the P-type epitaxial layer by controlling the evaporation power, evaporation temperature, and one or more methods in the oxygen atmosphere of the evaporation chamber during the evaporation process. , and then etch to form an ITO pattern to form a high-resistance ITO barrier layer.

[0076] Specifically, in this embodiment, combined with Figure 1A-1F Firstly, a high-resistance ITO film is formed on the P-type epitaxial layer 123 by evaporation, and a high-resistance ITO film can be formed by increasing the evaporation power, reducing the evaporation temperature, and increasing the oxygen atmosphere in the evaporation chambe...

Embodiment 3

[0080]The difference between this embodiment and Embodiment 1 is that while the ITO barrier layer 21 is formed on the P-type epitaxial layer 123 at the position corresponding to the P pad, an array of ITO barriers is also formed on the P-type epitaxial layer 123. The auxiliary layer 22 is extended. combine Figure 2A-2F As shown, in this embodiment, an ITO thin film is formed on the P-type epitaxial layer 123 by evaporation, and an ITO barrier layer pattern and an extended auxiliary layer pattern are simultaneously formed by photolithography and etching processes, and then a fluorine-containing solution is used Process the ITO barrier layer pattern and the extended auxiliary layer pattern, and carry out high-temperature annealing treatment to the ITO barrier layer pattern and the extended auxiliary layer pattern, so that the resistance of the ITO barrier layer pattern and the extended auxiliary layer pattern becomes large (conductivity variation) to simultaneously form the IT...

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Abstract

The invention provides an LED structure and a manufacturing method thereof. High-resistance-state ITO is arranged below a bonding pad P to serve as a barrier layer to improve the luminance of an LED chip, and due to the fact that extension electrodes and the barrier layer are both made of ITO, the phenomenon that the bonding pad P or the bonding pad P and the extension electrodes disengages / disengage from an LED die or disengages / disengage with the LED die at the same time during packaging and routing or during application in later period due to poor stickiness does not exist. Besides, due to the fact that the barrier layer is made of the high-resistance-state ITO, the barrier layer can be very thin, and the problems that the LED chip is high in voltage and poor in reliability due to the fact that the extension electrodes ITO become thinner on the periphery of the bonding pad P later are solved.

Description

technical field [0001] The invention belongs to the field of semiconductor optoelectronic chip manufacturing, and in particular relates to an LED structure and a manufacturing method thereof. Background technique [0002] Since its commercialization in the early 1990s, after more than 20 years of development, GaN-based LEDs have been widely used in indoor and outdoor display screens, lighting sources for projection displays, backlight sources, landscape lighting, advertising, traffic instructions, etc. Field, and known as the most competitive new generation of solid-state light source in the 21st century. However, for the semiconductor light-emitting device LED, in order to replace the traditional light source and enter the high-end lighting field, the problems of "three improvements and one reduction" of its key technology must be solved: namely, the problem of improving the brightness of the light, the problem of uniformity of the light, and the reliability of the device. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L33/58H01L33/48H01L33/00
CPCH01L33/005H01L33/42
Inventor 丁海生马新刚李东昇李芳芳江忠永
Owner HANGZHOU SILAN AZURE
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