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Core-less board manufacturing method

A manufacturing method and coreless board technology, which can be used in printed circuit manufacturing, multi-layer circuit manufacturing, semiconductor/solid-state device manufacturing, etc. The effect of increasing the pressing temperature and reducing the warpage

Active Publication Date: 2015-04-22
GUANGZHOU FASTPRINT CIRCUIT TECH +2
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the development of semiconductor packaging products in the direction of high performance, thinness and low cost, the coreless thin substrate technology has been born; because the coreless board is too thin, it will encounter serious warping problems, and it is easy to cause damage to the board during the production process. The problem of discarded pallets

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039]

Embodiment 2

[0041]

Embodiment 3

4.9mm

[0045] The warpage height refers to the height difference between the two ends of the coreless board; the warpage rate is the value of the height difference divided by the length of the board to represent the degree of warpage of the board.

[0046] The above examples all show that controlling the glass fiber thickness difference between the outer curing sheet and the inner curing sheet to be greater than 8 μm can effectively control the warpage rate below 1%, and the warpage height difference is not higher than 5mm. And the greater the difference in glass fiber thickness, the lower the warpage rate.

[0047] By asymmetrically adjusting and matching the glass fiber thickness and resin content of different layers of prepreg, the warpage reduction of the coreless board can be achieved simply and at low cost.

[0048] In addition, a double-layer glass fiber structure can also be arranged inside the outer curing sheet. The double-layer glass fiber structure inclu...

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Abstract

A core-less board manufacturing method comprises the steps that a supporting carrier is provided, inner copper foil layers are laminated on an upper accumulation layer of the supporting carrier, inner prepregs are arranged between all the inner copper foil layers, and outer copper foil layers are arranged outside outer prepregs to form a core-less board, wherein the highest temperature for laminating the inner copper foil layers and the inner prepregs ranges from 140 DEG C to 180 DEG C; the core-less board is separated from the supporting carrier. By the adoption of the core-less board manufacturing method, in the laminating process, pre-laminating is adopted for the inner prepregs and the inner copper foil layers, full-laminating is adopted for outer layers, and laminating temperature and laminating time are both improved. Compared with conventional laminating, the curing degree of the inner prepregs laminated through the laminating parameters of the method is only 70-95 percent of that of inner prepregs laminated through conventional parameters, full laminating parameters are adopted for laminating in the final laminating process of the outer layers, the residual stress on all the inner prepregs is lowered, and buckling of the core-less board is reduced.

Description

technical field [0001] The invention relates to the technical field of coreless panels, in particular to a method for manufacturing a coreless panel. Background technique [0002] With the development of semiconductor packaging products in the direction of high performance, thinness and low cost, the coreless thin substrate technology has been born; because the coreless board is too thin, it will encounter serious warping problems, and it is easy to cause damage to the board during the production process. The problem of discarded pallets. Contents of the invention [0003] Based on this, it is necessary to provide a coreless board manufacturing method to solve the warpage problem. [0004] A method for manufacturing a coreless board, comprising: providing a support carrier; laminating and laminating inner layer copper foils on the support carrier, with inner prepregs arranged between each inner layer copper foil layer, and then setting outer layer copper foil on the outsi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/58
CPCH05K3/42H05K3/46H05K3/4682H05K2203/06
Inventor 张志强李志东谢添华
Owner GUANGZHOU FASTPRINT CIRCUIT TECH
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