Method for manufacturing layers required by integrated circuit layout registration

Abstract

The invention discloses a method for manufacturing layers required by integrated circuit layout registration. The method includes the following steps that a data file of the gds format of an integrated circuit layout is introduced into planishing; a certain layer with process features is selected, and the layer is printed to form an electronic document file; the page margins of pages of picture files are set sequentially, graphs unrelated to the layout graphs are removed, only the layout graphs are reserved, and the adjacent layout graphs to be spliced are made to be right aligned with the page margins and are converted into a plurality of files of the jpeg format of the layer; the files of the jpeg format of the layer are selected, shapes of chip layouts are compared, the corresponding positions of the files of the jpeg format are set and are spliced into a graphic file; the spliced graphic file is evaluated; the manufactured files of all the layers are gathered to one file, and the layer files for the integrated circuit layout registration are formed. By means of the method, the splicing workload is lowered, the splicing accuracy is improved, and the requirement for layer manufacturing is met.

Description

[0001] technical field [0002] The invention relates to a method for making layers required for integrated circuit layout registration, and belongs to the technical field of integrated circuits. Background technique [0003] The registration of integrated circuit layout belongs to a kind of industrial property rights in intellectual property rights. During the registration, it is necessary to make graphics at each level. The graphics are generally obtained by taking screenshots of integrated circuit layouts and then manually splicing them. This method It is suitable for small-area layouts, but for layouts designed with deep submicron technology or large-area layouts, since there are requirements for the registered layout enlargement ratio, and the graphics must be clearly visible and undistorted when taking screenshots, manual The screenshot method needs to capture a lot of pictures, which leads to a lot of work when using manual stitching and the accuracy of graphic stitch...

AI Technical Summary

Problems solved by technology

[0003] The registration of integrated circuit layout belongs to a kind of industrial property rights in intellectual property rights. During the registration, it is necessary to make graphics at each level. The graphics are generally obtained by taking screenshots of integrated circuit layouts and then manually splicing them. This method It is suitable for small-area layouts, but for layouts designed with deep submicron technology or large-area layouts, since there are requirements for the registered layout enlargement ratio, and the graphics must be clearly visible and undistorted when taking screenshots, manual The screenshot method needs to capture a lot of pictures, which leads to a lot of work when using manual stitching and the accuracy of graphic stitching cannot be guaranteed. At the same time, due to the limitation of computer memory, it is impossible to handle a large amount of data stitching, and it is impossible to complete the corresponding layer. Graphical graphics, resulting in the inability to register and protect large-area integrated circuit layouts

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