Five-side packaged CSP (chip scale package) structure and manufacturing process

A manufacturing process and bread technology, which is applied in the field of CSP structure and manufacturing process of five-sided packaging, can solve problems such as reliability risks, and achieve the effect of simple manufacturing process and improved reliability

Inactive Publication Date: 2015-02-11
SHANGHAI FINE CHIP SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Ordinary WLCSP only uses bumps (Bumping) or copper pillars (Cu Pillar) as connections on the front of the wafer. The entire wafer is basically bare, without any material to protect the semiconductor die, and there is a risk of reliability.

Method used

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  • Five-side packaged CSP (chip scale package) structure and manufacturing process
  • Five-side packaged CSP (chip scale package) structure and manufacturing process
  • Five-side packaged CSP (chip scale package) structure and manufacturing process

Examples

Experimental program
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Effect test

Embodiment 1

[0030] see figure 1 , a five-sided encapsulation CSP structure given in the figure, including a crystal grain 10 and a pad 20 attached to the surface of the crystal 10, a passivation layer 30 and a conductor 40 attached to the pad 20, the passivation The layer 30 covers the area on the upper surface of the crystal grain 10 that is not covered by the pad 20 and the passivation layer 30 also covers the area of ​​the pad 20 that is not covered by the conductor 40, the bottom surface of the crystal grain 10 and the surrounding sides and passivation layer 30. The surrounding sides of the layer 30 are encapsulated by epoxy resin 50 .

[0031] The manufacturing process of the tube core of this embodiment specifically includes the following steps:

[0032] 1) Prepare the wafer;

[0033] 2) see figure 2 , on the first surface 110 of the wafer 100, a plurality of welding pads 20 and passivation layers 30 for packaging and bonding are attached at intervals, wherein the passivation la...

Embodiment 2

[0042] see Figure 10 , a five-sided encapsulation CSP structure given in the figure, including a crystal grain 10 and a pad 20 attached to the surface of the crystal 10, a passivation layer 30 and a conductor 40 attached to the pad 20, the passivation The layer 30 covers the area on the upper surface of the crystal grain 10 that is not covered by the pad 20 and the passivation layer 30 also covers the area of ​​the pad 20 that is not covered by the conductor 40 , and a metallization layer is provided on the back of the grain 10 60 , the bottom surface of the metallization layer 60 , the surrounding sides of the crystal grain 10 and the surrounding sides of the passivation layer 30 are encapsulated by the epoxy resin 50 .

[0043] The manufacturing process of the tube core of this embodiment specifically includes the following steps:

[0044] 1) Prepare the wafer;

[0045] 2) see Figure 11 , on the first surface 110 of the wafer 100, a plurality of welding pads 20 and pass...

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Abstract

The invention discloses a five-side packaged CSP (chip scale package) structure, which comprises a crystal particle, a press welding point, a passivation layer and a conducting body, wherein the press welding point is attached on the surface of the crystal particle, the conductor is attached on the press welding point, the passivation layer covers a region, not covered by the press welding point, on the upper surface of the crystal particle, and in addition, the passivation layer also covers a region, not covered by the conductor, of the press welding point. The five-side packaged CSP structure is characterized in that the bottom surface and the peripheral side surface of the crystal particle and the peripheral side surface of the passivation layer are packaged by epoxy resin. The invention also discloses a manufacturing process of the five-side packaged CSP structure. The five-side packaged CSP structure has the advantages that five sides (except the front side of a wafer) of a pipe core is packaged by the epoxy resin, the reliability of an electronic device and an integrated circuit can be favorably improved, in addition, WLCSP (wafer level chip scale package) packaging is adopted, and the miniaturization of an electronic product can be favorably realized. Meanwhile, the manufacturing process is simple and reliable.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to the CSP structure and manufacturing process of five-sided packaging Background technique [0002] Usually, semiconductor components and integrated circuits start to be packaged after the front-side process of the wafer is completed; usually the area of ​​the package is much larger than the area of ​​the chip, which is contrary to the current development trend of miniaturization; so later developed wafer-level packaging ( WLCSP). [0003] Ordinary WLCSP only uses bumps (Bumping) or copper pillars (Cu Pillar) as connections on the front side of the wafer. The entire wafer is basically bare, without any material to protect the semiconductor die, and there is a risk of reliability. . Contents of the invention [0004] One of the purposes of the present invention is to provide a five-sided CSP structure for the above-mentioned deficiencies in the prior art, which e...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L21/56
CPCH01L24/96H01L21/568H01L2224/94H01L2224/03
Inventor 杨凡力
Owner SHANGHAI FINE CHIP SEMICON
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