Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

PUF circuit based on threshold deviation delay

A delay circuit and deviation technology, applied in the field of physical unclonable function circuits, can solve problems such as high cost and inability to be reconfigured

Active Publication Date: 2015-01-28
NINGBO UNIV
View PDF5 Cites 24 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Since the unavoidable process deviation in the chip manufacturing process extracted by the PUF circuit is unique, the output key of the PUF circuit is constant and cannot be reconstructed. When the product (such as a chip) needs to change the password, it can only be The entire PUF hardware circuit is replaced, and the cost is very high

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • PUF circuit based on threshold deviation delay
  • PUF circuit based on threshold deviation delay
  • PUF circuit based on threshold deviation delay

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] Embodiment one: if figure 1 and figure 2 As shown, a physical unclonable function circuit based on threshold deviation delay includes a data input module 1, a controller 2, a decision device 3 and a PUF unit circuit 4. The input terminal of the data input module 1 is connected to external data, and the data input module The output end of 1 is connected with the input end of controller 2, and PUF unit circuit 4 comprises i-bit threshold value deviation delay circuit 5, and threshold value deviation delay circuit 5 is made up of two delay units, and two delay units are respectively first delay unit 6 and second delay unit 7;

[0021] like image 3 As shown, the delay unit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth The NMOS transistor N4 and the inverter, the source of the first PMOS transistor P1 ...

Embodiment 2

[0032] Embodiment 2: This embodiment is basically the same as Embodiment 1, the only difference is that in this embodiment, the decision device 3 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, a sixth NMOS transistor N6, The seventh NMOS transistor N7 and the eighth NMOS transistor N8, the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are connected to the power supply, the drain of the fifth PMOS transistor P5, the drain of the fifth NMOS transistor N5 pole, the drain of the sixth NMOS transistor N6, the gate of the sixth PMOS transistor P6 and the gate of the seventh NMOS transistor N7 are connected, the gate of the fifth PMOS transistor P5, the gate of the sixth NMOS transistor N6, the gate of the sixth NMOS transistor N6 The drain of the PMOS transistor P6, the drain of the seventh NMOS transistor N7 and the drain of the eighth NMOS transistor N8 are connected and the connection end is the ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a PUF (Physical Unclonable Functions) circuit based on threshold deviation delay. The PUF circuit comprises a data input module, a controller, a decision device and a PUF unit circuit, wherein external data is accessed into the input end of the data input module; the output end of the data input module is connected with the input end of the controller; the PUF unit circuit comprises an i-bit threshold deviation delay circuit; the threshold deviation delay circuit consists of two delay units; and the two delay units are respectively a first delay unit and a second delay unit. The PUF circuit has the advantages that the threshold deviation delay circuit is configured through control signals, so that a plurality of pieces of extractible process deviation exist in the PUF circuit; output signals (secret keys) of the PUF circuit can be reconstructed; and the output secret key change can be realized without replacing hardware.

Description

technical field [0001] The invention relates to a PUF circuit, in particular to a physical unclonable function circuit based on threshold deviation delay. Background technique [0002] With the development of integrated circuit technology and information security technology, people have higher and higher requirements for information security, and the development of high-performance security chips has become an urgent need of the information society. The Physical Unclonable Functions (PUF) circuit is a "DNA feature recognition technology" in the field of chips, which is unique, random and unclonable. a unique key. The above-mentioned characteristics of PUF circuits make it possible to defend against attacks. In multi-level security mechanisms, PUF circuits are used for key generation in public key encryption systems, smart card key identification systems, radio frequency identification (Radio Frequency IDentification, RFID) systems, and digital intellectual property protect...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/72
CPCG06F21/725
Inventor 张跃军汪鹏君李建瑞李刚
Owner NINGBO UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com