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High-precision phase-locked loop and phase locking method

A high-precision, phase-locked loop technology, applied in the electronic field, can solve the problems of phase lock instability and low phase lock precision, and achieve the effects of short lock time, high lock precision and avoiding phase transients

Inactive Publication Date: 2014-10-15
SUN YAT SEN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Aiming at the deficiencies in the prior art, the purpose of the present invention is to provide a high-precision phase-locked loop and a phase-locked method to solve the problems of unstable phase locking and low phase-locking precision in existing analog phase-locked loops

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  • High-precision phase-locked loop and phase locking method
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  • High-precision phase-locked loop and phase locking method

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Embodiment Construction

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are preferred implementation modes for implementing the present invention, and the description is for the purpose of illustrating the general principle of the present invention, and is not intended to limit the scope of the present invention. The scope of protection of the present invention should be defined by the claims. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection of the present invention. range.

[0031] see figure 2 , figure 2 It is a structural schematic diagram of an embodiment of the high-precision phase-locked loop of the present invention. exist figure 2 In the illustrated embodiment, the high-precision p...

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Abstract

The invention discloses a high-precision phase-locked loop comprising a frequency discriminator, a phase discriminator, a voltage-controlled oscillation module and a digital processing module. An input signal is inputted from the input ends of the phase discriminator and the frequency discriminator respectively. The output end of the frequency discriminator is connected with the digital processing module. The output end of the phase discriminator is connected with the input end of the voltage-controlled oscillation module. The input end of the voltage-controlled oscillation module is connected with the input end of the digital processing module. The output end of the digital processing module is connected with the feedback end of the phase discriminator. Frequency of an output signal is configured according to frequency of the input signal. Besides, phase difference between the input signals is adjusted via changing frequency change direction of the output signal so that the output signal is enabled to be matched with the input signal and an objective of phase locking is achieved.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a high-precision phase-locked loop and a phase-locked method. Background technique [0002] A Phase-Lock Loop (PLL for short) is a technique for synchronizing frequency and phase by using a feedback control principle. In some applications, the frequency and phase of an output clock signal (output signal) need to be synchronized with an external reference signal (input signal). When the frequency or phase of the input signal is detected to change, the phase-locked loop will detect this change and adjust the output signal through the internal feedback system until the input signal and the output signal are resynchronized. This synchronization is also called " Phase Locked”. At present, phase-locked loops are used in various fields, including: wireless communication systems, data and clock recovery circuits, frequency synthesis circuits, frequency-hopping communica...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/08H03L7/099
Inventor 王自鑫蔡志岗何振辉李泱元韦其敏颜奕王敏
Owner SUN YAT SEN UNIV
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