Electrostatic Discharge Protection Structure

Abstract

An electrostatic discharge protection structure, comprising: a P-type semiconductor substrate; a number of NMOS transistors arranged side by side on the surface of the P-type semiconductor substrate, a connection region and an N-type well region located in the P-type semiconductor substrate, the The N-type well region is at least located between the connection region and the NMOS transistor; the drain of the N-type well region and the NMOS transistor is connected to the electrostatic discharge input terminal, and the source of the NMOS transistor is connected to the ground terminal. Since the N-type well region is located at least between the connection region and the NMOS transistor, when the electrostatic voltage generated by the external electrostatic pulse is applied to the electrostatic discharge input terminal, the N-type well region will increase the substrate voltage of the NMOS transistor , so that the source and substrate of the NMOS transistor are easily turned on, which is beneficial to improving the conduction uniformity of the electrostatic discharge protection structure and improving the electrostatic protection capability.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to an electrostatic discharge protection structure. Background technique [0002] As semiconductor chips are used more and more widely, the electrostatic damage involved in semiconductor chips is also more and more extensive. There are many designs and applications of electrostatic discharge protection circuits, usually including: gate grounded N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit, diode protection circuit, silicon controlled rectifier (Silicon ControlledRectifier, SCR) protection circuit, etc. . [0003] Among them, the circuit diagram of the gate grounded N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit is as follows figure 1 As shown, the multiple gate-grounded N-type field effect transistors 10 are located between the external circuit 11 and the internal circuit 12 of the chip, and the drains of the gate...

AI Technical Summary

Problems solved by technology

However, due to layout design considerations, the existing ground connection area is generally located at the outermost side of the GGNMOS transistor, so that the parasitic resistances corresponding to different positions of the GGNMOS transistor in the prior art are different, so that the source and the substrate are close to the source and drain. The potential difference of the pole part is also different, and the parasitic NPN transistors formed by the source, substrate, and drain will not be turned on at the same time, so that the conduction uniformity of multiple GGNMOS transistors in the existing electrostatic discharge protection circuit is poor.

When some of the GGNMOS transistors are turned on, the others are not easy to turn on, which will seriously affect the ability of the electrostatic discharge protection circuit, which may cause the discharge current to be too high and burn out. Passing the GGNMOS transistor will not be able to play a protective role, reducing the ability of electrostatic protection

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