Electrostatic Discharge Protection Structure

Abstract

An electrostatic discharge protection structure, comprising: a semiconductor substrate; a plurality of N-type lateral diffusion field effect transistors arranged in parallel on the surface of the semiconductor substrate; a P-type body region located in the semiconductor substrate, and a source in the P-type body region Pole, channel region and body region connection region, the body region connection region is located on the outside of each N-type laterally diffused field effect transistor near the source; the drain of each N-type laterally diffused field effect transistor is connected to the electrostatic discharge input terminal , the source of each N-type laterally diffused field-effect transistor is connected to the ground terminal, the gate of each N-type laterally diffused field-effect transistor is connected to the first control voltage terminal, and each body region is connected to the second control voltage terminal. connected to the voltage terminals. A plurality of LDMOS transistors are connected together as an electrostatic discharge protection structure, which not only improves the electrostatic discharge capability, but also enables each parasitic triode to be turned on at the same time, thereby improving the conduction uniformity of the electrostatic discharge protection structure.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to an electrostatic discharge protection structure. Background technique [0002] As semiconductor chips are used more and more widely, the electrostatic damage involved in semiconductor chips is also more and more extensive. There are many designs and applications of electrostatic discharge protection circuits, usually including: gate grounded N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuit, silicon controlled rectifier (SCR) protection circuit, lateral diffusion field Effect transistor (Laterally Diffused MOS, LDMOS) protection circuit, etc. [0003] Please refer to figure 1 , is a structural schematic diagram of an electrostatic discharge protection structure formed by using LDMOS transistors in the prior art, specifically including: a P-type substrate 10, an N-type well region 11 located in the P-type substrate 10, and an N-type well region 11 located ...

AI Technical Summary

Problems solved by technology

However, the electrostatic discharge protection structure formed by the LDMOS transistor has low electrostatic discharge capability, which makes the electrostatic protection capability poor.

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