Writing method of nonvolatile memory unit array

Abstract

The invention discloses a writing method of a nonvolatile memory unit array. An array structure is optimized; when a writing operation is executed, a selected memory unit realizes a purpose of removing electrons in a floating gate through tunnelling effect to lower a threshold value by reasonable voltage configuration; a grid electrode and a drain electrode of the unselected memory unit do not exhibit a voltage difference which is big enough for realizing tunneling so as to guarantee that the threshold value of the memory unit is constant.

Description

field of invention [0001] The invention relates to the field of integrated circuits, in particular to providing a method for writing a non-volatile memory cell array in the field of memory. Background technique [0002] In the field of non-volatile memory, there are many different types of processes, circuits, and structures. Since the tunneling mechanism is easy to control the tunnel area, it can effectively reduce the risk of failure. Therefore, in the field that requires high reliability, erasing and Writing data is common, most typically in Electrically Erasable Read-Only Memory (EEPROM). Each of its memory cells contains two transistors, a select transistor, a floating-gate transistor, figure 1 The middle is a typical EEPROM memory cell, (a) is a schematic diagram, (b) is a structural diagram, and (c) is the voltage of the corresponding terminal during the erasing and writing operation. The memory cell injects or removes electrons in the floating gate through the tunn...

AI Technical Summary

Problems solved by technology

[0003] Electrically Erasable Read-Only Memory (EEPROM) technology is very mature, but because each memory cell requires two transistors, and both transistors need to meet the high-voltage resistance requirements, it is not easy to shrink the device area with process upgrades, thus Seriously restrict its wider application

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