Multistage cache consistency pipeline processing method and device

Abstract

The invention provides a multistage cache consistency pipeline processing method and device. The method comprises the steps that message information of currently-scheduled messages to be processed is obtained, wherein the message information comprises address information; whether the messages to be processed are effective messages is judged according to the message information, and if the messages to be processed are judged to be the effective messages, according to the address information in the message information, whether the effective messages which are unprocessed and have the same addresses as the messages to be processed exist is judged; if it is judged that the effective messages which are unprocessed and have the same addresses as the messages to be processed exist, the messages to be processed are blocked; if it is judged that the effective messages which are unprocessed and have the same addresses as the messages to be processed do not exist, cache consistency processing is carried out on the messages to be processed; by blocking the messages, to be processed, of the same addresses, when the cache consistency processing is carried out, resources are saved; moreover, timing sequence is good, and therefore the performance of a system is promoted.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method and device for processing a consistent multi-stage pipeline of a cache memory (Cache). Background technique [0002] During the development of computer technology, the access speed of the main memory has always been much slower than the operation speed of the central processing unit (CPU, Central Processing Unit), so that the high-speed processing capability of the central processing unit cannot be fully utilized. Cache is a high-speed small-capacity memory between the CPU and the main memory in the hierarchical structure of the computer storage system. Its capacity is generally only a few hundredths of the main memory, but its access speed can match that of the CPU. . According to the principle of program locality, there is a high probability that those units adjacent to a unit of main memory being used will be used. Therefore, when the CPU accesses a certain unit o...

AI Technical Summary

Problems solved by technology

In addition, there may also be resource and address conflicts in the process of Cache consistency maintenance, so there will be a large amount of chip resource usage and poor timing

If there are requests to the same address in a continuous period of time, and it is necessary to decouple all the messages processed on the pipeline, it will further occupy chip resources and cause poor timing, which restricts the increase of the chip system clock frequency, thus affecting the system. performance

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