Automatic frequency calibration circuit for sigma-delta fractional frequency synthesizer

Abstract

The invention discloses an automatic frequency calibration circuit for a sigma-delta fractional frequency synthesizer. The automatic frequency calibration circuit mainly comprises a 2M-divided frequency divider, a controlled counter, a comparator and a state machine, wherein the 2M-divided frequency synthesizer is used for controlling the running of the counter, the comparator and the state machine and the valid counting duration of the controlled counter, providing a sampling or working clock for the comparator and the state machine, and coordinating the time sequence relation between the comparator and the state machine; the comparator is used for comparing the reference of a frequency clock fREF and a feedback clock fDIV. The automatic frequency calibration circuit is at a rough calibration stage at a low level, and is at a fine calibration stage at a high level. At the rough calibration stage, the phase-locked loop of the frequency synthesizer is switched off, and the analog control end of a VCO (Voltage Control Oscillator) is connected with a fixed level. At the rough calibration stage, a result signal is at a low level, thus a sigma-delta decimal modulator is switched off, and the frequency error generated on the count value of the feedback clock fDIV by a decimal frequency dividing ratio part generated by the sigma-delta decimal modulator is lowered. At the fine calibration stage, the circuit runs normally.

Description

technical field [0001] The invention relates to an automatic frequency calibration circuit for a Σ-Δ (sigma-delta) fractional frequency synthesizer, belonging to the field of integrated circuit design. Background technique [0002] The ∑-△ fractional frequency synthesizer is the key module of the radio frequency front-end chip of the wireless transceiver. It can provide a stable, programmable, low-noise local oscillator clock for wireless transceivers of different standards. Its performance determines or affects the entire wireless transceiver system performance. Because its output clock has the advantages of high spectral purity, high operating frequency, low phase noise, low power consumption, and easy on-chip integration, it is widely used in academia and industry. [0003] Such as figure 1 As shown, it is a typical structural block diagram of ∑-△ fractional frequency synthesizer, which mainly includes the following components: frequency detector, phase detector, charge...

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that the N cnt The value is an approximate value, so the accuracy is not enough, and the best frequency adjustment curve may not always be selected during the frequency calibration process

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