Rising edge detection circuit

Abstract

The invention discloses a rising edge detection circuit which is composed of a bi-stable storage unit, an asymmetric delay unit, an inverter and a plurality of NMOS transistors. As long as an asymmetric delay circuit meets the conditions that the sum of rising edge delay and falling edge delay is larger than the pulse period of input signals and the falling edge delay is very small, output signals with the maximum pulse width close to the pulse period of the input signals can be generated, and the use requirements of a follow-up device can be met. The rising edge detection circuit not only is simple in structure, but also has a self starting function, and the self starting can be achieved when the initial low level length of the input signals is larger than the rising edge delay of the asymmetric delay circuit.

Description

technical field [0001] The invention relates to a rising edge detection circuit, in particular to a rising edge detection circuit whose output signal pulse width is greater than the input signal pulse width. Background technique [0002] The rising edge (or falling edge) detection circuit is a commonly used circuit, which is mainly used to detect whether there is a rising edge pulse in the input signal, and if so, output a pulse signal. The existing rising edge detection circuit consists of a delay unit, an inverter and an AND gate. One path of the input signal is directly connected to the AND gate, and the other path is connected to the AND gate after passing through a delay unit and an inverter in series. Assuming that the delays of the inverter and the AND gate are both zero, and the delay of the delay unit is the pulse width of the output pulse signal, the pulse width of the output pulse signal must be smaller than the pulse width of the input pulse signal, which cannot...

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Problems solved by technology

Assuming that the delays of the inverter and the AND gate are both zero, and the delay of the delay unit is the pulse width of the output pulse signal, the pulse width of the output pulse signal must be smaller than the pulse width of the input pulse signal, which cannot meet the requirements of the subsequent equipment for the output pulse signal. The pulse width is greater than the requirement of the pulse width of the input pulse signal

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