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Method for machining TI-IGBT chip back structure

A processing method and technology of backside structure, applied in the field of microelectronics, can solve the problems of individual design and production of TI-IGBT chips, and achieve the effects of improving consistency, saving plate-making costs, and reducing production costs.

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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a processing method for the back structure of a TI-IGBT chip, which solves the need to separately design and manufacture a corresponding back mask for exposing TI-IGBT chips of different voltage or current levels in the prior art board technical issues

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  • Method for machining TI-IGBT chip back structure
  • Method for machining TI-IGBT chip back structure
  • Method for machining TI-IGBT chip back structure

Examples

Experimental program
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Embodiment 1

[0035] In the embodiment of the present invention, an N-channel TI-IGBT is taken as an example, but it is also applicable to a P-channel TI-IGBT. It is only necessary to replace P / N with each other, which is the corresponding structure of P-channel TI-IGBT.

[0036] After the front process of the chip is completed, the back of the wafer is injected with P-type doping and then coated with photoresist on the back of the wafer. Then, according to the back mask plate, different areas are divided and exposed in sequence to form a back pattern;

[0037] The mask plate pattern contains a plurality of pattern units, and the pattern units are arranged symmetrically in translation; the relative position between the exposure areas is precisely controlled, so that the exposure pattern of the entire wafer is continuous and symmetrical in translation based on the pattern units; N-type doping is implanted on the back, and then the photoresist on the back is removed, and the back metallizati...

Embodiment 2

[0040] In addition, due to the lack of registration between the back graphics and the front graphics, it often results in a large (Nmax-Nmin) / (Nmax+Nmin), such as Figure 7The number of N+ collector regions contained on the back of chip A and chip B shown is quite different, and the parameter consistency for TI-IGBT is mainly related to the number of circular regions. If the number of N+ doped regions contained in different chips is very different (for example, the back of chip A contains 16 N+ doped regions, while the back of chip B only contains 9 N+ doped regions), it will inevitably lead to poor consistency of chip parameters .

[0041] see Figure 8 In order to reduce (Nmax-Nmin) / (Nmax+Nmin) as much as possible, an appropriate deflection angle can be formed between the arrangement direction of the graphic units on the back of the wafer and the arrangement direction of the chips on the front of the wafer. The calculation shows that (Nmax-Nmin) / (Nmax+Nmin) will change wit...

Embodiment 3

[0044] see Figure 10 , in order to further improve the consistency of parameters, the size of the chip can be matched with the cell size of the back pattern during design. Usually, chips with different voltages and current levels share the same back mask, that is to say, the size of the graphics unit on the back mask of the wafer is determined. In this way, the size of the chip on the front of the wafer is set as the unit of the graphics unit Integer multiples of the cell size. For the convenience of description, it is assumed that the graphics unit on the back of the wafer is a rectangle with a size of a×b. If the size of the chip is designed as ma×nb (m, n is a natural number), then although the graphics on the back are not aligned with the graphics on the front, the number of N+ collectors on the back of each chip is exactly the same, and the N+ collectors on the back of different chips The locations of the electrodes are exactly the same, which maximizes the consistency...

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Abstract

The invention discloses a method for machining a TI-IGBT chip back structure, and belongs to the technical field of the micro electronic. The method comprises the steps that after a wafer front structure is machined, P type doping is poured into the back face of a wafer; the back face of the wafer is coated with photoresist, and exposure is sequentially carried out on different areas, divided by a back mask plate, of the phototesist on the back face of the wafer, wherein the mask plate pattern comprises a plurality of pattern units symmetrically arranged in a horizontal movement mode; the relative position of the exposure areas is controlled, and the exposure patterns of the whole wafer are continuously symmetric in a horizontal movement mode based on the pattern units; N type doping is poured into the back face of the wafer after development, the photoresist on the back face is removed, and finally, back metallization is carried out after annealing activated doping. According to the method, TI-IGBT with different voltages and different current levels can share the same back mask plate, a large amount of plate making cost is saved, and production efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a method for exposing the back structure of a TI-IGBT chip. Background technique [0002] TI-IGBT: Triple mode Integrate-Insulated Gate Bipolar Transistor, triple mode integrated insulated gate bipolar transistor. It cleverly combines the structures and functions of IGBT, VDMOS and FRD. The device is similar to an IGBT device when it is conducting forward, and has a small conduction voltage drop. It is similar to VDMOS devices in the shutdown process and has a faster shutdown speed. When the device is subjected to reverse voltage, the device works like a FRD device. TI-IGBT devices can bidirectionally conduct current, and there is no need for anti-parallel freewheeling FRD when driving inductive loads. Compared with traditional IGBT devices, TI-IGBT improves the overall performance of the device on the one hand, and greatly reduces the manufacturing cost of the devic...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/331H01L21/027
CPCH01L21/0274H01L29/66333
Inventor 张文亮朱阳军高君宇
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