Simulation reading preprocessing circuit used for solid-state image sensor

Abstract

The invention provides a simulation reading preprocessing circuit used for a solid-state image sensor. The simulation reading preprocessing circuit comprises a correlated dual-sampling programmable gain amplification level shifting single-slippage switch capacitor network, an operational amplifier, a correlated level shifting network and a control signal generator, wherein the correlated dual-sampling programmable gain amplification level shifting single-slippage switch capacitor network is used for achieving collecting and preprocessing of signals output by a solid-state image sensor, the operational amplifier is used for achieving correlated dual-sampling, level shifting and single-slippage functions and functions of a programmable gain amplifier according to the virtual short circuit and charge conservation principle of two input ends of the operational amplifier, the correlated level shifting network is used for improving the equivalent gain of the operational amplifier and outputting final preprocessed signals, and the control signal generator is used for providing control signals. According to the simulation reading preprocessing circuit used for the solid-state image sensor, the CDS, PGA, LS and S2D circuit sharing operational amplifier technology is adopted, and functions of the simulation reading preprocessing circuit are achieved through the single operational amplifier, a switch and a capacitor.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an analog readout preprocessing circuit for a solid-state image sensor. Background technique [0002] Solid-state image sensors mainly include: CCD (Charge Coupled Device) and CIS (CMOS Image Sensor) image sensors. A solid-state image sensor with a resolution of M×N generally includes a pixel array (with a size of M×N), an analog readout processing circuit, and a digital control module. Among them, the size of the analog readout processing circuit is 1×P, 1≤P≤N; among them, P=1, serial readout, with the lowest parallelism, mainly used for low-speed image sensors; P=N, full-column parallel readout , with the highest degree of parallelism, mainly used for high-speed image sensors. The CCD image sensor pixel array is separately integrated with the analog readout processing circuit array and digital control module, while the CIS image sensor is monolithically integrated...

AI Technical Summary

Problems solved by technology

[0005] In the process of realizing the present invention, the applicant found that in the prior art analog readout preprocessing circuit, a high-gain operational amplifier is required, and as the process size shrinks, the intrinsic gain of the transistor decreases, and high-gain operation must be realized Amplifiers, which require multi-stage structures or operational amplifiers using gain-boosting techniques, these operational amplifiers are complex in structure, resulting in large area and power consumption

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