Multi-phase phase-locked loop circuit for clock data recovery

Abstract

The invention discloses a multiphase phase-locked loop used for clock data recovery. The multiphase phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a shift sequence generating circuit which are connected successively. The shift sequence generating circuit compares a control voltage output by the loop filter with two threshold voltages to obtain two shift signals, and the current of the charge pump, the resistance of the loop filter and the gain of the voltage controlled oscillator are dynamically changed via the two shift signals to dynamically adjust different parameters of the phase-locked loop. Thus, different input data whose speed changes extremely wide can be tracked in real time, a wider range of data transmission speeds can be tracked and locked, clock can be dynamically extracted from the input data of a wide range from 0 to 2Gbps, and further data synchronization and extraction are completed.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit method, in particular to a multi-phase phase-locked loop circuit for clock data recovery. Background technique [0002] Although the phase-locked loop (PLL) technology has been proposed for nearly 100 years, it is widely used in electronic systems, and at the same time, the performance requirements are getting higher and higher. The current PLL chip is developing towards the direction of high frequency, wide frequency bandwidth, large integration, low power consumption, low price, and powerful functions, but how to design a phase-locked loop circuit that can track a large range of input data is still quite challenging. . In the field of clock data recovery, due to the need to span a very wide data transmission rate range (0-Gbps), the existing single phase-locked loop cannot overcome such a wide rate range. Contents of the invention [0003] The technical problem to be solved by the presen...

AI Technical Summary

Problems solved by technology

The current PLL chip is developing towards the direction of high frequency, wide frequency bandwidth, large integration, low power consumption, low price, and powerful functions, but how to design a phase-locked loop circuit that can track a large range of input data is still quite challenging.

In the field of clock data recovery, due to the extremely wide data transmission rate range (0-Gbps) across the domain, the existing single phase-locked loop cannot overcome such a wide rate range

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