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Optimal method for correcting embedded memory

A technology of embedded memory and optimization method, applied in static memory, instruments, etc., can solve the problems of numerical fluctuation of electrical parameters, unstable device performance, etc., to improve the degree of numerical concentration, increase test time, and improve stability. Effect

Active Publication Date: 2014-06-04
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
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  • Claims
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Problems solved by technology

[0007] The present invention provides an optimization method for embedded memory correction to solve the problem in the prior art that after the embedded memory is corrected, the value of some electrical parameters will fluctuate around the specification value, resulting in unstable device performance

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  • Optimal method for correcting embedded memory
  • Optimal method for correcting embedded memory
  • Optimal method for correcting embedded memory

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Embodiment Construction

[0023] The optimization method for embedded memory modification proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will be more clear. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used for convenience and clarity to assist in explaining the present invention. Purpose of the example.

[0024] figure 2 A schematic flowchart of an optimization method for embedded memory correction provided by an embodiment of the present invention, as shown in figure 2 Shown, the optimization method of a kind of embedded memory correction that the present invention proposes, comprises the following steps:

[0025] Step S01: Correct the electrical parameters of the embedded memory, and determine the gear range;

[0...

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Abstract

The invention provides an optimal method for correcting an embedded memory. The optimal method comprises the steps of correcting an electric parameter of the embedded memory, and determining a gear range; reducing a gear from the left side and the right side within the determined gear range. Each gear is reduced from the left side and the right side within the gear range, so that the value concentration degree of the electric parameter is increased, values which fluctuate near to a set value are reduced, and the phenomenon that the value fluctuation exceeds the set value caused by factors such as design, manufacturing and test is avoided; therefore, the stability of the performance of a device is improved; meanwhile, the electric parameter does not need to be re-measured, so that the test time cannot be prolonged, and the performance stability is improved on the basis of guaranteeing the test efficiency.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to an optimization method for embedded memory correction. Background technique [0002] Semiconductor memory can be divided into two types: volatile memory and non-volatile memory. Volatile memory loses the stored data when the power is turned off, and non-volatile memory can protect the data even when the power is cut off. ROM is a non-volatile memory. ROM is divided into two types according to whether the user can write data. One is the ROM that the user can write, and the other is the one that the manufacturer writes during processing. ROM. Among the user-writable ROMs, EEPROM (Electrically Erasable Programmable ROM) and eflash (Embedded Flash Memory) are commonly used. [0003] Eflash is the product of the maturity of EEPROM, the development of semiconductor technology to sub-micron technology, and the demand for large-capacity electrically erasable memory. ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/44
Inventor 任栋梁吴玮桂伟钱亮
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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