FFT accelerator with high throughput rate

Abstract

The invention relates to an FFT accelerator with a high throughput rate. The FFT accelerator with the high throughput rate is characterized by comprising a data storage module, an address generation module and an FFT acceleration module, wherein the data storage module is used for reading, writing and transmission of data, the address generation module provides a target address of data transmission for the data storage module, and the FFT acceleration module carries out FFT on the data output by the data storage module. The FFT accelerator with the high throughput rate has the advantages that a one-way delayed feedback structure is adopted, the throughput rate is high, and the storage resources in a chip are effectively saved. The FFT accelerator supports expansion interface input on one hand, and supports ping-pong output on the other and. In the data input process, cache space is not needed, the data are fed into an FFT calculation component directly, and FFT calculation is carried out. In the data output process, inverted-order output is carried out through the cache.

Description

technical field [0001] The invention relates to an FFT accelerator, in particular to an FFT accelerator with high throughput. Background technique [0002] With the development of communication and radar technology, FFT has been widely used in fields such as wireless communication, speech recognition, image processing and spectrum analysis. Especially after the emergence of Orthogonal Frequency Division Multiplexing (OFDM), how to process large-point FFT faster and more flexibly has become an increasingly important issue. The FFT hardware architecture is mainly divided into two types: the FFT of the pipeline structure and the FFT of the memory structure. [0003] The FFT of the memory structure requires fewer storage units and computing units to consume hardware resources, but due to the FFT structure of the memory structure, the input and output of each level of data share the same block of RAM. Only when each frame of data is completely processed, The input of the next f...

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Problems solved by technology

[0003] The FFT of the memory structure requires fewer storage units and computing units to consume hardware resources, but due to the FFT structure of the memory structure, the input and output of each level of data share the same block of RAM. Only when each frame of data is completely processed, The input of the next frame of data can only be started, which increases the data transfer time, resulting in a decrease in data throughput and utilization of computing units

Therefore, the main disadvantage of the FFT of the memory structure is that it cannot perform continuous FFT data processing.

The existing FFT hardware structure is constrained by the on-chip storage resources, the operation efficiency is low, and the throughput rate is low

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