1-D/2-D hybrid architecture FFT (Fast Fourier Transform) processor

A hybrid architecture and processor technology, applied in complex mathematical operations and other directions, can solve the problems of large data storage resources and slow operation speed, and achieve the effect of less storage resources, improved speed, and high operation speed.

Active Publication Date: 2014-04-02
HEFEI UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] Finally, the above-mentioned one-dimensional (1-D) FFT processor has faster operation speed, but larger data storage resources
Two-dimensional (2-D) FFT processor can re

Method used

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  • 1-D/2-D hybrid architecture FFT (Fast Fourier Transform) processor
  • 1-D/2-D hybrid architecture FFT (Fast Fourier Transform) processor
  • 1-D/2-D hybrid architecture FFT (Fast Fourier Transform) processor

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Embodiment Construction

[0049] Such as image 3 As shown, the 1-D / 2-D hybrid architecture FFT processor in this embodiment includes a controller, a storage system, a data exchange network, a data transmission unit and an FFT calculation unit;

[0050] The controller is used to control the data transmission unit and the FFT operation unit;

[0051] The storage system includes 2 groups of 4*2K on-chip data memory (Memory0 / 1_x) and 3 groups of 4*32 temporary storage (Memory2 / 3 / 4_x), 2 groups of 4*2K on-chip data memory and 3 groups of 4*32 temporary storage Adopt simple dual-port RAM; according to 16K=128*128, the maximum one-dimensional FFT that needs to be processed in two-dimensional FFT processing mode is 128 points. In order to save storage resources, the FFT processor uses three groups of 4*32 temporary memory ping-pong operations to complete the ranks One-dimensional FFT operation.

[0052] The data exchange network includes an internal storage control unit, an external storage control unit and...

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Abstract

The invention discloses a 1-D/2-D hybrid architecture FFT processor, which is characterized in that the processor executes FFT or IFFT (Inverse Fast Fourier Transform) operation of any 2n point 32-bit single-precision floating point number from 32 point to 8K point through a one-dimensional FFT operation mode, executes FFT or IFFT operation of 16K point 32-bit single-precision floating point number through a two-dimensional operation mode, and realizes FFT/IFFT operation of any 2n point (n = 5, 6... 14) single-precision floating point number. The FFT processor provided by the invention carries out FFT or IFFT operation on data through a one-dimensional operation and two-dimensional operation hybrid mode, comprehensively considers FFT operation speed, storage resource consumption and flexibility, integrates the advantages of fast operation speed of the one-dimensional FFT processor and less storage resource of the two-dimensional FFT processor, and realizes balance between speed and resource.

Description

technical field [0001] The invention discloses a one-dimensional / two-dimensional (1-D / 2-D) hybrid architecture FFT processor, which belongs to the field of digital signal processing. Background technique [0002] At present, Fast Fourier Transform (FFT) is widely used in digital communication, image processing, speech recognition, radar processing and other fields. Hardware implementation of FFT has the incomparable speed advantage of software. It is based on Field Programmable Gate Array (FPGA) The method has important research value. The radix-2FFT algorithm is usually used to deal with length 2 n FFT operation of the signal. Because of its wide application and its own particularity, the fast Fourier transform of N-point base-2 requires its hardware to realize fast calculation speed and take into account the hardware area. There must be a good balance between the two. [0003] In the prior art, both the 1-D FFT processor and the 2-D large-point FFT processor can realize...

Claims

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Application Information

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IPC IPC(8): G06F17/14
Inventor 张多利黄路杜高明宋宇鲲贾靖华
Owner HEFEI UNIV OF TECH
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