A method of manufacturing a semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. The method comprises: providing a semiconductor substrate; successively forming an etching stop layer, a first dielectric layer, a second dielectric layer a hard mask layer and a metal hard mask layer on the substrate, wherein the second dielectric layer has a slower etching rate than the first dielectric layer; etching the metal hard mask layer to form an opening; and taking the metal hard mask layer as a mask layer to etch the hard mask layer, the second dielectric layer and the first dielectric layer to form a taper trench provided with a larger upper opening and an inclined side wall. According to the invention, in order to obtain better effects during trench filling, two ultra low K materials with different etching rates are arranged below a hard mask, the taper trench is formed by use of the different etching rates of the two in an etching process, and better filling effects can be obtained by use of the larger opening of the taper groove such that the problems of cavities and gaps easily occurring in the prior art are overcome.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, the present invention relates to a method for manufacturing a semiconductor device. Background technique [0002] With the continuous development of integrated circuit technology, more devices will be integrated on the chip, and the chip will adopt faster speed. Driven by these requirements, the geometric size of devices will continue to shrink, and new materials, new technologies and new manufacturing processes will be continuously used in the chip manufacturing process. As the size of semiconductor devices, such as CMOS devices, is reduced below 28nm, ultra-low K materials are usually used as interlayer dielectric layers in the back-end process to obtain better resistance and capacitance performance. [0003] In CMOS devices of 28nm and below, the dual damascene process is often used to form multilayer interconnection structures, that is, multilayer interconnection stru...

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Problems solved by technology

Wherein, after forming the trenches and via holes, when further filling conductive materials, since the metal hard mask has a high aspect ratio, it is easy to cause voids and voids during filling, which brings difficulties to filling.

[0004] In addition, not only in the dual damascene process, there is the problem that the gap is difficult to fill, but also in the filling after the formation of shallow trench isolation, resulting in a decrease in the yield of semiconductor devices. Therefore, it is necessary to improve the current process. Improve the trench and via filling effect

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