Preparation method for silicon-germanium heterojunction bipolar transistor (SiGe HBT)
A technology of heterojunction bipolar and manufacturing methods, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as external expansion and SiGeHBT performance deterioration, achieve good device performance, avoid re-diffusion, prevent Effects of Heterojunction Barrier Effects
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Embodiment 1
[0031] A method for manufacturing a germanium-silicon heterojunction bipolar transistor of the present invention comprises the following steps:
[0032] Step S01 , forming an N+ buried layer region in the silicon substrate, and forming an N− collector region on the N+ buried layer region.
[0033] see figure 1 with figure 2 Specifically, forming the N+ buried layer region 3 in the silicon substrate 1 includes: depositing a layer of first SiO on the silicon substrate 1 2 Layer 2: Etching the above-mentioned first SiO by dry etching and / or wet etching 2 layer 2 until the upper surface of the silicon substrate 1, in the first SiO 2 Form the window of N+ buried layer region 3 in layer 2; then ion-implant N-type impurities and anneal in a high-temperature furnace to obtain N+ buried layer region 3 located in silicon substrate 1, wherein the above-mentioned N-type impurities are phosphorus, arsenic or antimony . In this embodiment, the aforementioned silicon substrate 1 is a ...
Embodiment 2
[0051] A method for manufacturing a germanium-silicon heterojunction bipolar transistor of the present invention comprises the following steps:
[0052] Step S01 , forming an N+ buried layer region in the silicon substrate, and forming an N− collector region on the N+ buried layer region.
[0053] see figure 1 with figure 2 Specifically, forming the N+ buried layer region 3 in the silicon substrate 1 includes: depositing a layer of first SiO on the silicon substrate 1 2 Layer 2: Etching the above-mentioned first SiO by dry etching and / or wet etching 2 layer 2 until the upper surface of the silicon substrate 1, in the first SiO 2 Form the window of N+ buried layer region 3 in layer 2; then ion-implant N-type impurities and anneal in a high-temperature furnace to obtain N+ buried layer region 3 located in silicon substrate 1, wherein the above-mentioned N-type impurities are phosphorus or arsenic or antimony . In this embodiment, the aforementioned silicon substrate 1 is ...
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