Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A method for manufacturing a silicon-germanium heterojunction bipolar transistor

A technology of heterojunction bipolar and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of SiGeHBT performance deterioration, external expansion, etc., to avoid re-diffusion, good device performance, prevent The Effect of Heterojunction Barrier Effect

Active Publication Date: 2018-08-10
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since the boron atoms in the P-type base region will expand during the later thermal annealing process, and the redistribution of boron will lead to the heterojunction barrier effect of the heterojunction, which will lead to a sharp deterioration in the performance of SiGe HBT

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A method for manufacturing a silicon-germanium heterojunction bipolar transistor
  • A method for manufacturing a silicon-germanium heterojunction bipolar transistor
  • A method for manufacturing a silicon-germanium heterojunction bipolar transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] A method for manufacturing a germanium-silicon heterojunction bipolar transistor of the present invention comprises the following steps:

[0032] Step S01 , forming an N+ buried layer region in the silicon substrate, and forming an N− collector region on the N+ buried layer region.

[0033] see figure 1 and figure 2 Specifically, forming the N+ buried layer region 3 in the silicon substrate 1 includes: depositing a layer of first SiO on the silicon substrate 1 2 Layer 2: Etching the above-mentioned first SiO by dry etching and / or wet etching 2 layer 2 until the upper surface of the silicon substrate 1, in the first SiO 2 Form the window of N+ buried layer region 3 in layer 2; then ion-implant N-type impurities and anneal in a high-temperature furnace to obtain N+ buried layer region 3 located in silicon substrate 1, wherein the above-mentioned N-type impurities are phosphorus or arsenic or antimony . In this embodiment, the aforementioned silicon substrate 1 is a...

Embodiment 2

[0051] A method for manufacturing a germanium-silicon heterojunction bipolar transistor of the present invention comprises the following steps:

[0052] Step S01 , forming an N+ buried layer region in the silicon substrate, and forming an N− collector region on the N+ buried layer region.

[0053] see figure 1 with figure 2 Specifically, forming the N+ buried layer region 3 in the silicon substrate 1 includes: depositing a layer of first SiO on the silicon substrate 1 2 Layer 2: Etching the above-mentioned first SiO by dry etching and / or wet etching 2 layer 2 until the upper surface of the silicon substrate 1, in the first SiO 2 Form the window of N+ buried layer region 3 in layer 2; then ion-implant N-type impurities and anneal in a high-temperature furnace to obtain N+ buried layer region 3 located in silicon substrate 1, wherein the above-mentioned N-type impurities are phosphorus or arsenic or antimony . In this embodiment, the aforementioned silicon substrate 1 is ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a preparation method for a SiGe HBT. N type impurities are implanted in ions into a second polysilicon layer, and then annealing with laser in a proper wavelength, instead of normal rapid thermal annealing, is used to activate the N type impurities; and thus, energy of the laser in the proper wavelength only has effect within the thickness range of the second polysilicon layer, and does not influence a SiGe base region under the second polysilicon layer. Therefore, on the premise that the N type impurities which are implanted in ions into the second polysilicon layer are effectively activated, boron in the SiGe base region is avoided form further spreading, further barrier effect of heterojunction is prevented, and the SiGe HBT has better performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor device preparation, in particular to a method for manufacturing a germanium-silicon heterojunction bipolar transistor. Background technique [0002] In recent years, due to the performance of silicon-germanium heterojunction transistors with energy band engineering characteristics is significantly better than that of bipolar transistors, silicon-germanium heterojunction transistors have been developed rapidly. The energy band structure of the NPN-type germanium-silicon heterojunction bipolar transistor (SiGeHeterojunction Bipolar Transistor, referred to as SiGe HBT) suppresses the injection of holes in the base region to the emitter region, and facilitates the injection of electrons in the emitter region into the base region. Therefore, the injection efficiency of the emitter region is improved, so that the current gain is mainly determined by the energy band instead of only by the impurity ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/737H01L29/06H01L21/331H01L21/265
CPCH01L21/268H01L29/66242
Inventor 周伟张伟严利人刘志弘付军周卫王全
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com