Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device which comprises a substrate, a plurality of grid stacking structures, a plurality of grid sidewall structures and a plurality of source-drain regions. The grid stacking structures are arranged on the substrate. The two sides of each grid stacking structure are provided with the grid sidewall structures. The positions, on the two sides of each grid sidewall structure, of the substrate are provided with the source-drain regions. The grid stacking structures comprise a plurality of first grid stacking structures and a plurality of second grid stacking structures. The semiconductor device is characterized in that each first grid stacking structure comprises a first grid insulation layer, a first blocking layer, a first work function regulating layer and a resistance regulating layer, and each second grid stacking structure comprises a second grid insulation layer, the first blocking layer, a second work function regulating layer, the first work function regulating layer and the resistance regulating layer. According to the semiconductor device and a manufacturing method thereof, firstly, an NMOS work function regulating layer is selectively deposited, and then a PMOS work function regulating layer is deposited. Consequently, a PMOS metal grid structure is simplified, metal grid work functions are effectively controlled, meanwhile, the filled spaces of the resistance regulating layers are enlarged, and the grid resistance is effectively reduced.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a CMOS with more effective control of work function and reduced gate resistance and a manufacturing method thereof. Background technique [0002] Starting from the 45nm CMOS integrated circuit process, with the continuous reduction of device feature size, in order to suppress the short channel effect, the equivalent oxide thickness (EOT) of the gate insulating dielectric layer in CMOS devices must be reduced simultaneously. However, due to the low (relative) dielectric constant (for example, about 3.9) of the ultra-thin (eg 10nm) conventional oxide layer or oxynitride layer, the insulation performance is difficult to withstand the relatively high field strength in such ultra-small devices, which will cause serious damage. gate leakage. Therefore, the traditional polysilicon (poly-si) / SiON system is no longer applicable. [0003] In view of this, the i...

AI Technical Summary

Problems solved by technology

In this way, in the device structure of the PMOS region, the metal gate structure is extremely complex (containing three barrier layers), and under the condition that the feature size-gate length is gradually reduced, especially when the gate length is below 22nm, at this time due to many The structure of the layer barrier layer reduces the space that can be filled by the resistance adjustment layer in the PMOS region, and there are problems that the resistance adjustment layer is small and difficult to effectively reduce the gate resistance, and insufficient filling causes holes to increase the resistivity.

Images