Method for extracting trap time constant of gate dielectric layer of semiconductor device

Abstract

The invention discloses a method for extracting the trap time constant of a gate dielectric layer of a semiconductor device, belonging to the field of microelectronic device reliability. The method comprises the steps of firstly, initializing the trap state in the semiconductor device so that the final state of a trap is an empty state; then, applying a direct current (DC) signal or an alternating current (AC) signal to a gate terminal, and controlling a drain terminal to be zero-bias Vd1; after a period of time t1, respectively applying low voltage Vg2 and Vd2 onto the gate terminal and the drain terminal, and detecting the state of leak current Id; changing the time t1 to be t2 which is the sum of t1 and delta t, keeping other conditions unchanged, repeating the previous step under the condition that, and so on; after the measurement is carried out for N times, obtaining the current states of the drain terminal corresponding to the N time points t1, t1+ delta t,... t1+(N-1) delta t; finally, carrying out moving average and working out occupation probabilities P corresponding to (N-n) moment points; utilizing formula fitting to obtain the capture time constant and the launch time constant of the trap.

Description

technical field [0001] The invention belongs to the field of reliability of microelectronic devices, and relates to a method for extracting trap time constants in gate dielectric layers of small-scale semiconductor devices. Background technique [0002] With the gradual reduction of the scale of semiconductor devices, the number of traps in the gate dielectric layer is gradually reduced, which makes the random behavior of traps more and more attention, and the influence of electrical characteristics caused by a single trap in small-sized devices It is far greater than the impact of traps in large-scale devices; it will cause serious impacts in the circuit, for example, it will increase the delay of some logic circuits, and the read failure of static random access memory (SRAM), etc. Therefore, research on small-size The behavior of traps in devices, a comprehensive grasp of the basic characteristics of traps is of great significance for predicting the degradation characteris...

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Problems solved by technology

For a certain gate voltage, there may be a situation where the two time constants have a large difference in magnitude, so the above method is limited by the test time and the storage capacity of the test instrument and it is difficult to realize; however, this situation is also an important research category. Therefore, it is necessary to realize the test of the trap time constant through other effective methods, especially to solve the above-mentioned problems, and then support the research on the trap behavior

In this regard, the current method basically obtains the occupancy probability of multiple time points through testing, and then fits the model to obtain the time constant; however, this method is inefficient, and a large amount of test data can meet certain accuracy requirements. Therefore, It is necessary to propose an efficient method for testing and extracting trap time constants that meets the accuracy requirements

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