Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure. The semiconductor structure comprises a substrate, a gate stack, source / drain areas and STI structures, wherein the gate stack is located on the substrate and comprises at least a gate medium layer and a gate electrode layer, the source / drain areas are located in the portions, arranged at the two sides of the gate stack, of the substrate, the STI structures are located in the portions, arranged at the two sides of the source / drain areas, of the substrate, and according to the type of the semiconductor structure, the shape of the section of each STI structure is a regular trapezoid or a Sigma shape or a reverse trapezoid. Correspondingly, the invention further provides a manufacturing method of the semiconductor structure. According to the semiconductor structure, through the combination of the STI structures of different shapes and fillers with different kinds of stress, different kinds of tensile stress or pressure stress on a channel can be generated in the transverse direction, so that positive influence on the electron mobility of an NMOS and the hole mobility of a PMOS is generated, and the channel current of a device is increased. Therefore, the performance of the semiconductor structure is effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor device manufacturing technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space of each component, between components or each component itself need to be further reduced (currently can reach the nanoscale). Starting from the 90nm CMOS integrated circuit process, with the continuous shrinking of the device feature size, the channel stress process (Strain Channel Engineering) for the purpose of improving the channel carrier mobility has played an increasingly important role. Various uniaxial process induced stresses are integrated into the device process. [0003] Typically, STI (Shallow Trench Isolation) processes such as liner generation, dielectric filling, an...

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Problems solved by technology

This will cause compressive strain in the longitudinal direction of the channel, which in turn will lead to an increase in PMOS mobility and a decrease in NMOS mobility

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