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Address generator of heterogeneous multi-core processor

A multi-core processor and address generator technology, applied in the field of multi-core processors, can solve the problems of inflexible address generation, inability to meet complex algorithm processing requirements, and single address calculation method, so as to improve automatic processing capabilities. , Improve the efficiency of address generation and the effect of expanding the scope of applications

Active Publication Date: 2013-10-23
BEIJING MXTRONICS CORP +1
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AI Technical Summary

Problems solved by technology

[0009] The traditional address generator can only complete the simple addition and subtraction of addresses, and its calculation method is single. Some address generators with DSP processors have the functions of bit flip addressing and circular addressing, but they cannot satisfy complex Algorithm processing requirements, in addition, there is also a lack of flexibility in the address generation method

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  • Address generator of heterogeneous multi-core processor
  • Address generator of heterogeneous multi-core processor
  • Address generator of heterogeneous multi-core processor

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Embodiment Construction

[0056] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0057] When heterogeneous multi-core is used for real-time digital signal processing, different algorithms in digital signal processing require different read and write address rules, so the address generator is required to support some complex address generation methods, such as fft operations. The present invention designs a three-layer cyclic address generation method, which can satisfy the addressing of conventional fft operation data and twiddle factors, and can also realize incremental sequential addressing and limited number of cyclic addressing. The address addressing of the three-level loop mode means that the first level of loop is based on the base address and increases according to the configured fixed step size 1 to generate a configured number of addresses; the second level of loop controls the number of cycles of the first level of...

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Abstract

The invention relates to an address generator of a heterogeneous multi-core processor, which comprises a bit turnover addressing module, a cyclic addressing module, a sequential addressing module, a three-layer cyclic addressing module, a configurable register set, a control logic module and a data selector. Addressing can be performed according to bit turnover addressing, cyclic addressing, sequential addressing and three-layer cyclic address generation modes; addresses can be generated according to a configured clock interval period; addressing of data of the conventional fft (Fast Fourier Transform) algorithm and a twiddle factor can be met; incremental sequential addressing and cyclic addressing of finite length can also be achieved; an application scope of the address generator is expanded; the capacity of complex algorithm processing is improved effectively; and the performance of a multi-core system chip is improved greatly.

Description

technical field [0001] The invention relates to an address generator of a heterogeneous multi-core processor, belonging to the technical field of multi-core processors. Background technique [0002] With the development of microelectronics technology, multi-core processors have become the mainstream development direction. Multi-core processors, also known as single-chip multi-processors, improve the performance of processors by integrating multiple micro-cores within a single chip. [0003] There are many architectures for multi-core processors, among which single-bus architecture and grid architecture are the main ones. With multi-core bus structure, when the number of cores increases to a certain number, the performance often cannot be increased accordingly, which hinders the growth of the number of cores in the chip. The multi-core feature of the grid architecture is that the cores are connected through programmable switches, which is scalable, greatly improves the inte...

Claims

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Application Information

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IPC IPC(8): G06F15/167G06F12/02
Inventor 亓洪亮宋立国盖辰宁于立新
Owner BEIJING MXTRONICS CORP
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