Method for manufacturing ultra-thin ruthenium film by aid of plasma enhanced atomic layer deposition process

Abstract

The invention belongs to the technical field of copper interconnection processes for very-large-scale integrated circuits, and particularly relates to a method for manufacturing an ultra-thin ruthenium film by the aid of a plasma enhanced atomic layer deposition process. The method includes using double (ethyl cyclopentadienyl) ruthenium (II) as a precursor and adjusting the exposure time of oxygen plasmas to acquire pure ruthenium metal by the aid of the plasma enhanced atomic layer deposition process. The method has the advantages that the growth thickness of the ultra-thin ruthenium film can be precisely controlled in a nanometer scale by the aid of the plasma enhanced atomic layer deposition process, the ultra-thin ruthenium film is good in copper adhesiveness and excellent in copper insolubility during plating, trenches and through holes can be prevented from generating cavities, and seedless crystal copper plating can be implemented.

Description

technical field [0001] The invention belongs to the technical field of ultra-large-scale integrated circuit copper interconnection technology, and specifically relates to a method for preparing an ultra-thin ruthenium film by using a plasma-enhanced atomic layer deposition technology. Background technique [0002] In the copper interconnect technology of modern integrated circuits, an effective barrier layer must not only prevent copper from diffusing into the dielectric layer, but also improve the adhesion between the barrier layer and the dielectric layer. As we all know, in the 0.13 micron technology node, the tantalum / tantalum nitride (Ta / TaN) double-layer barrier layer has been successfully used in industrial copper interconnection technology. However, as the minimum feature size of integrated circuits is gradually reduced to 45 nanometers, the Ta / TaN double-layer barrier layer is facing many problems. For example, the proportional reduction of the barrier layer and the...

AI Technical Summary

Problems solved by technology

[0003] However, with the further development of integrated circuit technology, the feature size of semiconductor devices continues to shrink. When the minimum feature size of integrated circuits gradually shrinks to 32 nanometers or below, this structure will face various challenges

With the large increase in the aspect ratio of trenches and vias, it is difficult to scale down the diffusion barrier layer and seed copper layer sputtered by physical vapor deposition (PVD), and the step coverage becomes poor, which may Can cause voiding in trenches and vias

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