Device and method for extracting high-resolution depth map in real time based on image matching
A high-resolution, extraction device technology, applied in image communication, electrical components, stereo systems, etc., can solve the problems of low efficiency of 3DTV depth extraction, can not meet real-time applications, etc., to achieve functional updates, easy to carry and install, and easy to upgrade. Effect
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Embodiment 1
[0028] refer to figure 1 , a device for real-time extraction of high-resolution depth maps based on image matching, including a binocular SDI camera (1) and an FPGA development board (2), characterized in that the binocular SDI camera (1) is unidirectionally connected to the FPGA development board (2), the FPGA development board is unidirectionally connected to a 3DTV encoding server (3); the binocular SDI camera (1) is used to acquire images, and the depth real-time extraction is realized on the FPGA development board (2), and the real-time transmission of the depth map is obtained to the 3DTV encoding server.
Embodiment 2
[0030] This embodiment is basically the same as Embodiment 1, and the special feature is: the binocular SDI camera adopts Panasonic AG-3DA1MC binocular high-definition camera. The camera can output high-definition video through SDI, and the two channels of video have undergone image correction and can be directly stereo matched. The FPGA development board adopts EP2AGX260 FPGA chip, and the chip is bidirectionally connected to 1GB DDR2 SODIMM as a data buffer module. The front end of the FPGA development board is designed with two SDI receiving modules. The LMH0344 equalizer performs DC recovery on the SDI signal. The LMH0341 deserializer automatically detects the input data rate and extracts the clock; The image is output to the 3DTV encoding server.
Embodiment 3
[0032] This high-resolution depth map real-time extraction method based on image matching uses the above-mentioned device for real-time extraction of the depth map. The special feature is that it is realized by designing a digital circuit in the FPGA chip. The operation steps are as follows:
[0033] Ⅰ. SDI analysis: analyze the two synchronous SDI video inputs after deserialization into video data signals;
[0034] Ⅱ. Matching cost estimation: Realize the construction of matching cost function and the estimation of matching cost by means of digital circuit;
[0035]Ⅲ. WTA Optimal Selection-Generate Depth Map: Select the optimal match within the parallax range in a digital circuit.
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