Low density parity check (LDPC) decoder and implementation method thereof
A decoder and codeword technology, applied in the direction of using block codes for error correction/detection, applying multi-bit parity bit error detection coding, data representation error detection/correction, etc., can solve the problem of wasting chip resources in storage space, Large storage space, many computing units, etc., to achieve the effect of saving chip resources, reducing storage space, and reducing computing units
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[0083] The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0084] figure 1 It is a schematic structural diagram of an LDPC decoder of the present invention. Such as figure 1 As shown, an LDPC decoder of the present invention at least includes an input buffer unit 11 , a state control and address generation module 12 , a check node processing module 13 , a variable node processing module 14 and a decision code word storage unit 15 .
[0085] Where...
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