Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device comprises: a semiconductor substrate; a channel region on the semiconductor substrate, the channel region comprising a quantum well structure; a source region and a drain region on two sides of the channel region; a gate structure on the channel region. The energy bands of the materials of the channel region, the source region, and the drain region are different from each other. A tunneling barrier structure exists between the source region and the channel region.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof. Background technique [0002] In the past few decades, the scaling technology of MOS devices has made CMOS integrated circuit technology greatly improved in terms of performance and speed. Moore's Law describes the law that the number of transistors per unit area of ​​a chip doubles every 18 months and has continued so far. With the in-depth development of integrated circuit technology, in the process of continuous scaling down of CMOS technology, the power consumption and operating voltage of its MOS devices cannot continue to decrease in the same proportion, various parasitic effects, performance degradation and reliability problems Also gradually serious. Especially when the channel is reduced to the nanometer range, the bulk silicon MOS device is close to the physical limit, and there are serious problems such as short channel effect, reduced mobility, and the lim...

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Problems solved by technology

Figure 1c It is a narrow-band homogeneous p-i-n tunneling structure, its tunneling efficiency is improved, the driving current is increased, SS<40mV / dec, the working voltage is about 0.4V, and the reverse leakage is large

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